6b9c26fb5e
In the Release 6 of the MIPS Architecture, LL, SC, LLD, SCD, PREF and CACHE instructions have 9 bits offsets. Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> |
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.. | ||
libvixl | ||
alpha.c | ||
arm-a64.cc | ||
arm.c | ||
cris.c | ||
hppa.c | ||
i386.c | ||
ia64.c | ||
lm32.c | ||
m68k.c | ||
Makefile.objs | ||
microblaze.c | ||
mips.c | ||
moxie.c | ||
ppc.c | ||
s390.c | ||
sh4.c | ||
sparc.c | ||
tci.c |