Ivan Klokov 6bca4d7d1f target/riscv/cpu_helper.c: Fix mxr bit behavior ... According to RISCV Specification sect 9.5 on two stage translation when V=1 the vsstatus(mstatus in QEMU's terms) field MXR, which makes execute-only pages readable, only overrides VS-stage page protection. Setting MXR at HS-level(mstatus_hs), however, overrides both VS-stage and G-stage execute-only permissions. The hypervisor extension changes the behavior of MXR\MPV\MPRV bits. Due to RISCV Specification sect. 9.4.1 when MPRV=1, explicit memory accesses are translated and protected, and endianness is applied, as though the current virtualization mode were set to MPV and the current nominal privilege mode were set to MPP. vsstatus.MXR makes readable those pages marked executable at the VS translation stage. Fixes: 36a18664ba ("target/riscv: Implement second stage MMU") Signed-off-by: Ivan Klokov <ivan.klokov@syntacore.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20231121071757.7178-3-ivan.klokov@syntacore.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2023-11-22 14:03:37 +10:00
..
insn_trans	target/riscv: Replace Zvbb checking by Zvkb	2023-11-07 11:06:02 +10:00
kvm	target/riscv/kvm: add zicsr, zifencei, zba, zbs, svnapot	2023-11-07 11:06:02 +10:00
tcg	target/riscv: don't verify ISA compatibility for zicntr and zihpm	2023-11-22 13:56:13 +10:00
arch_dump.c
bitmanip_helper.c
common-semi-target.h
cpu_bits.h	target/riscv: Add M-mode virtual interrupt and IRQ filtering support.	2023-11-07 11:02:17 +10:00
cpu_cfg.h	target/riscv: Add "pmu-mask" property to replace "pmu-num"	2023-11-07 11:06:02 +10:00
cpu_helper.c	target/riscv/cpu_helper.c: Fix mxr bit behavior	2023-11-22 14:03:37 +10:00
cpu_user.h
cpu_vendorid.h
cpu-param.h
cpu-qom.h	target: Move ArchCPUClass definition to 'cpu.h'	2023-11-07 13:08:48 +01:00
cpu.c	hw/cpu: Call object_class_is_abstract() once in cpu_class_by_name()	2023-11-07 13:08:48 +01:00
cpu.h	target/riscv/cpu.h: spelling fix: separatly	2023-11-15 12:06:05 +03:00
crypto_helper.c
csr.c	target/riscv: Don't assume PMU counters are continuous	2023-11-07 11:06:02 +10:00
debug.c
debug.h
fpu_helper.c
gdbstub.c	target/riscv: rename ext_icsr to ext_zicsr	2023-11-07 11:02:17 +10:00
helper.h
insn16.decode
insn32.decode
instmap.h
internals.h	target/riscv: Use env_archcpu() in [check_]nanbox()	2023-11-07 12:13:27 +01:00
Kconfig
m128_helper.c
machine.c	target/riscv: Add "pmu-mask" property to replace "pmu-num"	2023-11-07 11:06:02 +10:00
meson.build	target/riscv: move KVM only files to kvm subdir	2023-10-12 12:20:24 +10:00
monitor.c
op_helper.c
pmp.c	target/riscv: pmp: Ignore writes when RW=01	2023-11-07 11:06:02 +10:00
pmp.h	target/riscv: pmp: Clear pmp/smepmp bits on reset	2023-11-07 11:06:02 +10:00
pmu.c	target/riscv: Add "pmu-mask" property to replace "pmu-num"	2023-11-07 11:06:02 +10:00
pmu.h	target/riscv: Use existing PMU counter mask in FDT generation	2023-11-07 11:06:02 +10:00
riscv-qmp-cmds.c	target/riscv/riscv-qmp-cmds.c: check CPU accel in query-cpu-model-expansion	2023-11-07 11:06:02 +10:00
sbi_ecall_interface.h
time_helper.c
time_helper.h
trace-events
trace.h
translate.c	accel/tcg: Replace CPUState.env_ptr with cpu_env()	2023-10-04 11:03:54 -07:00
vcrypto_helper.c
vector_helper.c	target/riscv: Fix vfwmaccbf16.vf	2023-10-12 12:50:13 +10:00
vector_internals.c
vector_internals.h
xthead.decode
XVentanaCondOps.decode
zce_helper.c