qemu-e2k/accel
Peter Maydell 62c0ac5041 Adjust types for some memory access functions.
Reduce inclusion of tcg headers.
 Fix watchpoints vs replay.
 Fix tcg/aarch64 roli expansion.
 Introduce SysemuCPUOps structure.
 -----BEGIN PGP SIGNATURE-----
 
 iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmCu3TodHHJpY2hhcmQu
 aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV9ibwf+IyI2B3CrrJUkyzdg
 AiKasEQJS7XoKRf924THegSHQEzFltDEuOiSdq3x2oFB9iMuZeu/HH/CLdw3qCFb
 IZgsFhhYRjtzO6aVanyNWE2/b3HViGPI4rRvk09YaQg+FEEKqCw6Qb+MM3yv9Aa2
 7VGsYX1u0RK/W6CfgUFULcnjbKUcPtOnZRZZMiNKwA6Jg9m19ASAVuLCmoQrcIg7
 PrpGUuSn8VrC3ICGcqALbCVp+HWcMERuckAlSJ3cOvAng+vcvxSy8lkUm5sibkm2
 27k+t2IzwTObVlyVKj2TvLC3GVXHg/0juXg7UH1h1+cshn0BIX5HuzDU8NyMj+Dj
 RHeoqA==
 =RPLq
 -----END PGP SIGNATURE-----

Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20210526' into staging

Adjust types for some memory access functions.
Reduce inclusion of tcg headers.
Fix watchpoints vs replay.
Fix tcg/aarch64 roli expansion.
Introduce SysemuCPUOps structure.

# gpg: Signature made Thu 27 May 2021 00:43:54 BST
# gpg:                using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg:                issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A  05C0 64DF 38E8 AF7E 215F

* remotes/rth-gitlab/tags/pull-tcg-20210526: (31 commits)
  hw/core: Constify TCGCPUOps
  target/mips: Fold jazz behaviour into mips_cpu_do_transaction_failed
  cpu: Move CPUClass::get_paging_enabled to SysemuCPUOps
  cpu: Move CPUClass::get_memory_mapping to SysemuCPUOps
  cpu: Move CPUClass::get_phys_page_debug to SysemuCPUOps
  cpu: Move CPUClass::asidx_from_attrs to SysemuCPUOps
  cpu: Move CPUClass::write_elf* to SysemuCPUOps
  cpu: Move CPUClass::get_crash_info to SysemuCPUOps
  cpu: Move CPUClass::virtio_is_big_endian to SysemuCPUOps
  cpu: Move CPUClass::vmsd to SysemuCPUOps
  cpu: Introduce SysemuCPUOps structure
  cpu: Move AVR target vmsd field from CPUClass to DeviceClass
  cpu: Rename CPUClass vmsd -> legacy_vmsd
  cpu: Assert DeviceClass::vmsd is NULL on user emulation
  cpu: Directly use get_memory_mapping() fallback handlers in place
  cpu: Directly use get_paging_enabled() fallback handlers in place
  cpu: Directly use cpu_write_elf*() fallback handlers in place
  cpu: Introduce cpu_virtio_is_big_endian()
  cpu: Un-inline cpu_get_phys_page_debug and cpu_asidx_from_attrs
  cpu: Split as cpu-common / cpu-sysemu
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-05-28 16:25:21 +01:00
..
hvf hvf: Add hypervisor entitlement to output binaries 2021-01-29 10:47:28 +00:00
kvm KVM: Dirty ring support 2021-05-26 14:49:46 +02:00
qtest accel: replace struct CpusAccel with AccelOpsClass 2021-02-05 10:24:15 -10:00
stubs Do not include cpu.h if it's not really necessary 2021-05-02 17:24:51 +02:00
tcg accel/tcg: Keep TranslationBlock headers local to TCG 2021-05-26 15:33:59 -07:00
xen sysemu: Let VMChangeStateHandler take boolean 'running' argument 2021-03-09 23:13:57 +01:00
accel-common.c accel: add init_accel_cpu for adapting accel behavior to CPU type 2021-05-10 15:41:52 -04:00
accel-softmmu.c accel: replace struct CpusAccel with AccelOpsClass 2021-02-05 10:24:15 -10:00
accel-softmmu.h accel: replace struct CpusAccel with AccelOpsClass 2021-02-05 10:24:15 -10:00
accel-user.c accel: extend AccelState and AccelClass to user-mode 2021-02-05 10:24:15 -10:00
dummy-cpus.c accel: move qtest CpusAccel functions to a common location 2020-10-24 07:23:19 +02:00
Kconfig Add NVMM accelerator: configure and build logic 2021-05-04 14:15:34 +02:00
meson.build accel: extend AccelState and AccelClass to user-mode 2021-02-05 10:24:15 -10:00