1067 lines
30 KiB
C
1067 lines
30 KiB
C
#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include "cpu.h"
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#include "exec-all.h"
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static inline void set_feature(CPUARMState *env, int feature)
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{
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env->features |= 1u << feature;
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}
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static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
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{
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env->cp15.c0_cpuid = id;
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switch (id) {
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case ARM_CPUID_ARM926:
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set_feature(env, ARM_FEATURE_VFP);
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env->vfp.xregs[ARM_VFP_FPSID] = 0x41011090;
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env->cp15.c0_cachetype = 0x1dd20d2;
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env->cp15.c1_sys = 0x00090078;
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break;
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case ARM_CPUID_ARM946:
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set_feature(env, ARM_FEATURE_MPU);
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env->cp15.c0_cachetype = 0x0f004006;
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env->cp15.c1_sys = 0x00000078;
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break;
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case ARM_CPUID_ARM1026:
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set_feature(env, ARM_FEATURE_VFP);
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set_feature(env, ARM_FEATURE_AUXCR);
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env->vfp.xregs[ARM_VFP_FPSID] = 0x410110a0;
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env->cp15.c0_cachetype = 0x1dd20d2;
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env->cp15.c1_sys = 0x00090078;
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break;
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case ARM_CPUID_TI915T:
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case ARM_CPUID_TI925T:
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set_feature(env, ARM_FEATURE_OMAPCP);
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env->cp15.c0_cpuid = ARM_CPUID_TI925T; /* Depends on wiring. */
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env->cp15.c0_cachetype = 0x5109149;
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env->cp15.c1_sys = 0x00000070;
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env->cp15.c15_i_max = 0x000;
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env->cp15.c15_i_min = 0xff0;
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break;
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case ARM_CPUID_PXA250:
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case ARM_CPUID_PXA255:
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case ARM_CPUID_PXA260:
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case ARM_CPUID_PXA261:
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case ARM_CPUID_PXA262:
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set_feature(env, ARM_FEATURE_XSCALE);
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/* JTAG_ID is ((id << 28) | 0x09265013) */
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env->cp15.c0_cachetype = 0xd172172;
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env->cp15.c1_sys = 0x00000078;
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break;
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case ARM_CPUID_PXA270_A0:
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case ARM_CPUID_PXA270_A1:
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case ARM_CPUID_PXA270_B0:
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case ARM_CPUID_PXA270_B1:
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case ARM_CPUID_PXA270_C0:
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case ARM_CPUID_PXA270_C5:
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set_feature(env, ARM_FEATURE_XSCALE);
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/* JTAG_ID is ((id << 28) | 0x09265013) */
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set_feature(env, ARM_FEATURE_IWMMXT);
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env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
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env->cp15.c0_cachetype = 0xd172172;
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env->cp15.c1_sys = 0x00000078;
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break;
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default:
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cpu_abort(env, "Bad CPU ID: %x\n", id);
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break;
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}
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}
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void cpu_reset(CPUARMState *env)
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{
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uint32_t id;
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id = env->cp15.c0_cpuid;
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memset(env, 0, offsetof(CPUARMState, breakpoints));
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if (id)
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cpu_reset_model_id(env, id);
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#if defined (CONFIG_USER_ONLY)
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env->uncached_cpsr = ARM_CPU_MODE_USR;
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env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30;
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#else
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/* SVC mode with interrupts disabled. */
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env->uncached_cpsr = ARM_CPU_MODE_SVC | CPSR_A | CPSR_F | CPSR_I;
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env->vfp.xregs[ARM_VFP_FPEXC] = 0;
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#endif
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env->regs[15] = 0;
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tlb_flush(env, 1);
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}
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CPUARMState *cpu_arm_init(void)
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{
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CPUARMState *env;
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env = qemu_mallocz(sizeof(CPUARMState));
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if (!env)
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return NULL;
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cpu_exec_init(env);
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cpu_reset(env);
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return env;
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}
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struct arm_cpu_t {
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uint32_t id;
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const char *name;
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};
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static const struct arm_cpu_t arm_cpu_names[] = {
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{ ARM_CPUID_ARM926, "arm926"},
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{ ARM_CPUID_ARM946, "arm946"},
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{ ARM_CPUID_ARM1026, "arm1026"},
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{ ARM_CPUID_TI925T, "ti925t" },
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{ ARM_CPUID_PXA250, "pxa250" },
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{ ARM_CPUID_PXA255, "pxa255" },
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{ ARM_CPUID_PXA260, "pxa260" },
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{ ARM_CPUID_PXA261, "pxa261" },
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{ ARM_CPUID_PXA262, "pxa262" },
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{ ARM_CPUID_PXA270, "pxa270" },
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{ ARM_CPUID_PXA270_A0, "pxa270-a0" },
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{ ARM_CPUID_PXA270_A1, "pxa270-a1" },
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{ ARM_CPUID_PXA270_B0, "pxa270-b0" },
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{ ARM_CPUID_PXA270_B1, "pxa270-b1" },
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{ ARM_CPUID_PXA270_C0, "pxa270-c0" },
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{ ARM_CPUID_PXA270_C5, "pxa270-c5" },
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{ 0, NULL}
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};
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void arm_cpu_list(FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...))
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{
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int i;
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(*cpu_fprintf)(f, "Available CPUs:\n");
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for (i = 0; arm_cpu_names[i].name; i++) {
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(*cpu_fprintf)(f, " %s\n", arm_cpu_names[i].name);
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}
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}
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void cpu_arm_set_model(CPUARMState *env, const char *name)
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{
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int i;
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uint32_t id;
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id = 0;
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i = 0;
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for (i = 0; arm_cpu_names[i].name; i++) {
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if (strcmp(name, arm_cpu_names[i].name) == 0) {
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id = arm_cpu_names[i].id;
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break;
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}
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}
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if (!id) {
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cpu_abort(env, "Unknown CPU '%s'", name);
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return;
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}
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cpu_reset_model_id(env, id);
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}
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void cpu_arm_close(CPUARMState *env)
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{
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free(env);
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}
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#if defined(CONFIG_USER_ONLY)
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void do_interrupt (CPUState *env)
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{
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env->exception_index = -1;
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}
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int cpu_arm_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
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int mmu_idx, int is_softmmu)
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{
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if (rw == 2) {
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env->exception_index = EXCP_PREFETCH_ABORT;
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env->cp15.c6_insn = address;
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} else {
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env->exception_index = EXCP_DATA_ABORT;
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env->cp15.c6_data = address;
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}
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return 1;
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}
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target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
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{
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return addr;
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}
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/* These should probably raise undefined insn exceptions. */
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void helper_set_cp(CPUState *env, uint32_t insn, uint32_t val)
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{
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int op1 = (insn >> 8) & 0xf;
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cpu_abort(env, "cp%i insn %08x\n", op1, insn);
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return;
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}
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uint32_t helper_get_cp(CPUState *env, uint32_t insn)
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{
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int op1 = (insn >> 8) & 0xf;
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cpu_abort(env, "cp%i insn %08x\n", op1, insn);
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return 0;
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}
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void helper_set_cp15(CPUState *env, uint32_t insn, uint32_t val)
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{
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cpu_abort(env, "cp15 insn %08x\n", insn);
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}
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uint32_t helper_get_cp15(CPUState *env, uint32_t insn)
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{
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cpu_abort(env, "cp15 insn %08x\n", insn);
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return 0;
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}
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void switch_mode(CPUState *env, int mode)
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{
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if (mode != ARM_CPU_MODE_USR)
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cpu_abort(env, "Tried to switch out of user mode\n");
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}
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#else
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extern int semihosting_enabled;
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/* Map CPU modes onto saved register banks. */
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static inline int bank_number (int mode)
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{
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switch (mode) {
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case ARM_CPU_MODE_USR:
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case ARM_CPU_MODE_SYS:
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return 0;
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case ARM_CPU_MODE_SVC:
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return 1;
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case ARM_CPU_MODE_ABT:
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return 2;
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case ARM_CPU_MODE_UND:
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return 3;
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case ARM_CPU_MODE_IRQ:
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return 4;
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case ARM_CPU_MODE_FIQ:
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return 5;
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}
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cpu_abort(cpu_single_env, "Bad mode %x\n", mode);
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return -1;
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}
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void switch_mode(CPUState *env, int mode)
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{
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int old_mode;
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int i;
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old_mode = env->uncached_cpsr & CPSR_M;
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if (mode == old_mode)
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return;
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if (old_mode == ARM_CPU_MODE_FIQ) {
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memcpy (env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t));
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memcpy (env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t));
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} else if (mode == ARM_CPU_MODE_FIQ) {
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memcpy (env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t));
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memcpy (env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t));
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}
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i = bank_number(old_mode);
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env->banked_r13[i] = env->regs[13];
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env->banked_r14[i] = env->regs[14];
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env->banked_spsr[i] = env->spsr;
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i = bank_number(mode);
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env->regs[13] = env->banked_r13[i];
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env->regs[14] = env->banked_r14[i];
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env->spsr = env->banked_spsr[i];
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}
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/* Handle a CPU exception. */
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void do_interrupt(CPUARMState *env)
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{
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uint32_t addr;
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uint32_t mask;
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int new_mode;
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uint32_t offset;
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/* TODO: Vectored interrupt controller. */
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switch (env->exception_index) {
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case EXCP_UDEF:
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new_mode = ARM_CPU_MODE_UND;
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addr = 0x04;
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mask = CPSR_I;
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if (env->thumb)
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offset = 2;
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else
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offset = 4;
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break;
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case EXCP_SWI:
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if (semihosting_enabled) {
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/* Check for semihosting interrupt. */
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if (env->thumb) {
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mask = lduw_code(env->regs[15] - 2) & 0xff;
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} else {
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mask = ldl_code(env->regs[15] - 4) & 0xffffff;
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}
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/* Only intercept calls from privileged modes, to provide some
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semblance of security. */
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if (((mask == 0x123456 && !env->thumb)
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|| (mask == 0xab && env->thumb))
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&& (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
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env->regs[0] = do_arm_semihosting(env);
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return;
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}
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}
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new_mode = ARM_CPU_MODE_SVC;
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addr = 0x08;
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mask = CPSR_I;
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/* The PC already points to the next instructon. */
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offset = 0;
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break;
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case EXCP_PREFETCH_ABORT:
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case EXCP_BKPT:
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new_mode = ARM_CPU_MODE_ABT;
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addr = 0x0c;
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mask = CPSR_A | CPSR_I;
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offset = 4;
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break;
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case EXCP_DATA_ABORT:
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new_mode = ARM_CPU_MODE_ABT;
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addr = 0x10;
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mask = CPSR_A | CPSR_I;
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offset = 8;
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break;
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case EXCP_IRQ:
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new_mode = ARM_CPU_MODE_IRQ;
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addr = 0x18;
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/* Disable IRQ and imprecise data aborts. */
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mask = CPSR_A | CPSR_I;
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offset = 4;
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break;
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case EXCP_FIQ:
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new_mode = ARM_CPU_MODE_FIQ;
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addr = 0x1c;
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/* Disable FIQ, IRQ and imprecise data aborts. */
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mask = CPSR_A | CPSR_I | CPSR_F;
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offset = 4;
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break;
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default:
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cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);
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return; /* Never happens. Keep compiler happy. */
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}
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/* High vectors. */
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if (env->cp15.c1_sys & (1 << 13)) {
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addr += 0xffff0000;
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}
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switch_mode (env, new_mode);
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env->spsr = cpsr_read(env);
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/* Switch to the new mode, and switch to Arm mode. */
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/* ??? Thumb interrupt handlers not implemented. */
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env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode;
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env->uncached_cpsr |= mask;
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env->thumb = 0;
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env->regs[14] = env->regs[15] + offset;
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env->regs[15] = addr;
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env->interrupt_request |= CPU_INTERRUPT_EXITTB;
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}
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/* Check section/page access permissions.
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Returns the page protection flags, or zero if the access is not
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permitted. */
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static inline int check_ap(CPUState *env, int ap, int domain, int access_type,
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int is_user)
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{
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if (domain == 3)
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return PAGE_READ | PAGE_WRITE;
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switch (ap) {
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case 0:
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if (access_type == 1)
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return 0;
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switch ((env->cp15.c1_sys >> 8) & 3) {
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case 1:
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return is_user ? 0 : PAGE_READ;
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case 2:
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return PAGE_READ;
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default:
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return 0;
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}
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case 1:
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return is_user ? 0 : PAGE_READ | PAGE_WRITE;
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case 2:
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if (is_user)
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return (access_type == 1) ? 0 : PAGE_READ;
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else
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return PAGE_READ | PAGE_WRITE;
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case 3:
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return PAGE_READ | PAGE_WRITE;
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default:
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abort();
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}
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}
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static int get_phys_addr(CPUState *env, uint32_t address, int access_type,
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int is_user, uint32_t *phys_ptr, int *prot)
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{
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int code;
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uint32_t table;
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uint32_t desc;
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int type;
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int ap;
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int domain;
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uint32_t phys_addr;
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|
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/* Fast Context Switch Extension. */
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if (address < 0x02000000)
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address += env->cp15.c13_fcse;
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if ((env->cp15.c1_sys & 1) == 0) {
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/* MMU/MPU disabled. */
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*phys_ptr = address;
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*prot = PAGE_READ | PAGE_WRITE;
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} else if (arm_feature(env, ARM_FEATURE_MPU)) {
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int n;
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uint32_t mask;
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uint32_t base;
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*phys_ptr = address;
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for (n = 7; n >= 0; n--) {
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base = env->cp15.c6_region[n];
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if ((base & 1) == 0)
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continue;
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mask = 1 << ((base >> 1) & 0x1f);
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/* Keep this shift separate from the above to avoid an
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(undefined) << 32. */
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mask = (mask << 1) - 1;
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if (((base ^ address) & ~mask) == 0)
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break;
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}
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if (n < 0)
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return 2;
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|
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if (access_type == 2) {
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mask = env->cp15.c5_insn;
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} else {
|
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mask = env->cp15.c5_data;
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}
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mask = (mask >> (n * 4)) & 0xf;
|
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switch (mask) {
|
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case 0:
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return 1;
|
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case 1:
|
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if (is_user)
|
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return 1;
|
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*prot = PAGE_READ | PAGE_WRITE;
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break;
|
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case 2:
|
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*prot = PAGE_READ;
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if (!is_user)
|
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*prot |= PAGE_WRITE;
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break;
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case 3:
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*prot = PAGE_READ | PAGE_WRITE;
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break;
|
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case 5:
|
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if (is_user)
|
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return 1;
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*prot = PAGE_READ;
|
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break;
|
|
case 6:
|
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*prot = PAGE_READ;
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break;
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default:
|
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/* Bad permission. */
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return 1;
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}
|
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} else {
|
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/* Pagetable walk. */
|
|
/* Lookup l1 descriptor. */
|
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table = (env->cp15.c2_base & 0xffffc000) | ((address >> 18) & 0x3ffc);
|
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desc = ldl_phys(table);
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type = (desc & 3);
|
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domain = (env->cp15.c3 >> ((desc >> 4) & 0x1e)) & 3;
|
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if (type == 0) {
|
|
/* Secton translation fault. */
|
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code = 5;
|
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goto do_fault;
|
|
}
|
|
if (domain == 0 || domain == 2) {
|
|
if (type == 2)
|
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code = 9; /* Section domain fault. */
|
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else
|
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code = 11; /* Page domain fault. */
|
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goto do_fault;
|
|
}
|
|
if (type == 2) {
|
|
/* 1Mb section. */
|
|
phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
|
|
ap = (desc >> 10) & 3;
|
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code = 13;
|
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} else {
|
|
/* Lookup l2 entry. */
|
|
if (type == 1) {
|
|
/* Coarse pagetable. */
|
|
table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
|
|
} else {
|
|
/* Fine pagetable. */
|
|
table = (desc & 0xfffff000) | ((address >> 8) & 0xffc);
|
|
}
|
|
desc = ldl_phys(table);
|
|
switch (desc & 3) {
|
|
case 0: /* Page translation fault. */
|
|
code = 7;
|
|
goto do_fault;
|
|
case 1: /* 64k page. */
|
|
phys_addr = (desc & 0xffff0000) | (address & 0xffff);
|
|
ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
|
|
break;
|
|
case 2: /* 4k page. */
|
|
phys_addr = (desc & 0xfffff000) | (address & 0xfff);
|
|
ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
|
|
break;
|
|
case 3: /* 1k page. */
|
|
if (type == 1) {
|
|
if (arm_feature(env, ARM_FEATURE_XSCALE))
|
|
phys_addr = (desc & 0xfffff000) | (address & 0xfff);
|
|
else {
|
|
/* Page translation fault. */
|
|
code = 7;
|
|
goto do_fault;
|
|
}
|
|
} else
|
|
phys_addr = (desc & 0xfffffc00) | (address & 0x3ff);
|
|
ap = (desc >> 4) & 3;
|
|
break;
|
|
default:
|
|
/* Never happens, but compiler isn't smart enough to tell. */
|
|
abort();
|
|
}
|
|
code = 15;
|
|
}
|
|
*prot = check_ap(env, ap, domain, access_type, is_user);
|
|
if (!*prot) {
|
|
/* Access permission fault. */
|
|
goto do_fault;
|
|
}
|
|
*phys_ptr = phys_addr;
|
|
}
|
|
return 0;
|
|
do_fault:
|
|
return code | (domain << 4);
|
|
}
|
|
|
|
int cpu_arm_handle_mmu_fault (CPUState *env, target_ulong address,
|
|
int access_type, int mmu_idx, int is_softmmu)
|
|
{
|
|
uint32_t phys_addr;
|
|
int prot;
|
|
int ret, is_user;
|
|
|
|
is_user = mmu_idx == MMU_USER_IDX;
|
|
ret = get_phys_addr(env, address, access_type, is_user, &phys_addr, &prot);
|
|
if (ret == 0) {
|
|
/* Map a single [sub]page. */
|
|
phys_addr &= ~(uint32_t)0x3ff;
|
|
address &= ~(uint32_t)0x3ff;
|
|
return tlb_set_page (env, address, phys_addr, prot, mmu_idx,
|
|
is_softmmu);
|
|
}
|
|
|
|
if (access_type == 2) {
|
|
env->cp15.c5_insn = ret;
|
|
env->cp15.c6_insn = address;
|
|
env->exception_index = EXCP_PREFETCH_ABORT;
|
|
} else {
|
|
env->cp15.c5_data = ret;
|
|
env->cp15.c6_data = address;
|
|
env->exception_index = EXCP_DATA_ABORT;
|
|
}
|
|
return 1;
|
|
}
|
|
|
|
target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
|
|
{
|
|
uint32_t phys_addr;
|
|
int prot;
|
|
int ret;
|
|
|
|
ret = get_phys_addr(env, addr, 0, 0, &phys_addr, &prot);
|
|
|
|
if (ret != 0)
|
|
return -1;
|
|
|
|
return phys_addr;
|
|
}
|
|
|
|
void helper_set_cp(CPUState *env, uint32_t insn, uint32_t val)
|
|
{
|
|
int cp_num = (insn >> 8) & 0xf;
|
|
int cp_info = (insn >> 5) & 7;
|
|
int src = (insn >> 16) & 0xf;
|
|
int operand = insn & 0xf;
|
|
|
|
if (env->cp[cp_num].cp_write)
|
|
env->cp[cp_num].cp_write(env->cp[cp_num].opaque,
|
|
cp_info, src, operand, val);
|
|
}
|
|
|
|
uint32_t helper_get_cp(CPUState *env, uint32_t insn)
|
|
{
|
|
int cp_num = (insn >> 8) & 0xf;
|
|
int cp_info = (insn >> 5) & 7;
|
|
int dest = (insn >> 16) & 0xf;
|
|
int operand = insn & 0xf;
|
|
|
|
if (env->cp[cp_num].cp_read)
|
|
return env->cp[cp_num].cp_read(env->cp[cp_num].opaque,
|
|
cp_info, dest, operand);
|
|
return 0;
|
|
}
|
|
|
|
/* Return basic MPU access permission bits. */
|
|
static uint32_t simple_mpu_ap_bits(uint32_t val)
|
|
{
|
|
uint32_t ret;
|
|
uint32_t mask;
|
|
int i;
|
|
ret = 0;
|
|
mask = 3;
|
|
for (i = 0; i < 16; i += 2) {
|
|
ret |= (val >> i) & mask;
|
|
mask <<= 2;
|
|
}
|
|
return ret;
|
|
}
|
|
|
|
/* Pad basic MPU access permission bits to extended format. */
|
|
static uint32_t extended_mpu_ap_bits(uint32_t val)
|
|
{
|
|
uint32_t ret;
|
|
uint32_t mask;
|
|
int i;
|
|
ret = 0;
|
|
mask = 3;
|
|
for (i = 0; i < 16; i += 2) {
|
|
ret |= (val & mask) << i;
|
|
mask <<= 2;
|
|
}
|
|
return ret;
|
|
}
|
|
|
|
void helper_set_cp15(CPUState *env, uint32_t insn, uint32_t val)
|
|
{
|
|
uint32_t op2;
|
|
uint32_t crm;
|
|
|
|
op2 = (insn >> 5) & 7;
|
|
crm = insn & 0xf;
|
|
switch ((insn >> 16) & 0xf) {
|
|
case 0: /* ID codes. */
|
|
if (arm_feature(env, ARM_FEATURE_XSCALE))
|
|
break;
|
|
if (arm_feature(env, ARM_FEATURE_OMAPCP))
|
|
break;
|
|
goto bad_reg;
|
|
case 1: /* System configuration. */
|
|
if (arm_feature(env, ARM_FEATURE_OMAPCP))
|
|
op2 = 0;
|
|
switch (op2) {
|
|
case 0:
|
|
if (!arm_feature(env, ARM_FEATURE_XSCALE) || crm == 0)
|
|
env->cp15.c1_sys = val;
|
|
/* ??? Lots of these bits are not implemented. */
|
|
/* This may enable/disable the MMU, so do a TLB flush. */
|
|
tlb_flush(env, 1);
|
|
break;
|
|
case 1:
|
|
if (arm_feature(env, ARM_FEATURE_XSCALE)) {
|
|
env->cp15.c1_xscaleauxcr = val;
|
|
break;
|
|
}
|
|
goto bad_reg;
|
|
case 2:
|
|
if (arm_feature(env, ARM_FEATURE_XSCALE))
|
|
goto bad_reg;
|
|
env->cp15.c1_coproc = val;
|
|
/* ??? Is this safe when called from within a TB? */
|
|
tb_flush(env);
|
|
break;
|
|
default:
|
|
goto bad_reg;
|
|
}
|
|
break;
|
|
case 2: /* MMU Page table control / MPU cache control. */
|
|
if (arm_feature(env, ARM_FEATURE_MPU)) {
|
|
switch (op2) {
|
|
case 0:
|
|
env->cp15.c2_data = val;
|
|
break;
|
|
case 1:
|
|
env->cp15.c2_insn = val;
|
|
break;
|
|
default:
|
|
goto bad_reg;
|
|
}
|
|
} else {
|
|
env->cp15.c2_base = val;
|
|
}
|
|
break;
|
|
case 3: /* MMU Domain access control / MPU write buffer control. */
|
|
env->cp15.c3 = val;
|
|
tlb_flush(env, 1); /* Flush TLB as domain not tracked in TLB */
|
|
break;
|
|
case 4: /* Reserved. */
|
|
goto bad_reg;
|
|
case 5: /* MMU Fault status / MPU access permission. */
|
|
if (arm_feature(env, ARM_FEATURE_OMAPCP))
|
|
op2 = 0;
|
|
switch (op2) {
|
|
case 0:
|
|
if (arm_feature(env, ARM_FEATURE_MPU))
|
|
val = extended_mpu_ap_bits(val);
|
|
env->cp15.c5_data = val;
|
|
break;
|
|
case 1:
|
|
if (arm_feature(env, ARM_FEATURE_MPU))
|
|
val = extended_mpu_ap_bits(val);
|
|
env->cp15.c5_insn = val;
|
|
break;
|
|
case 2:
|
|
if (!arm_feature(env, ARM_FEATURE_MPU))
|
|
goto bad_reg;
|
|
env->cp15.c5_data = val;
|
|
break;
|
|
case 3:
|
|
if (!arm_feature(env, ARM_FEATURE_MPU))
|
|
goto bad_reg;
|
|
env->cp15.c5_insn = val;
|
|
break;
|
|
default:
|
|
goto bad_reg;
|
|
}
|
|
break;
|
|
case 6: /* MMU Fault address / MPU base/size. */
|
|
if (arm_feature(env, ARM_FEATURE_MPU)) {
|
|
if (crm >= 8)
|
|
goto bad_reg;
|
|
env->cp15.c6_region[crm] = val;
|
|
} else {
|
|
if (arm_feature(env, ARM_FEATURE_OMAPCP))
|
|
op2 = 0;
|
|
switch (op2) {
|
|
case 0:
|
|
env->cp15.c6_data = val;
|
|
break;
|
|
case 1:
|
|
env->cp15.c6_insn = val;
|
|
break;
|
|
default:
|
|
goto bad_reg;
|
|
}
|
|
}
|
|
break;
|
|
case 7: /* Cache control. */
|
|
env->cp15.c15_i_max = 0x000;
|
|
env->cp15.c15_i_min = 0xff0;
|
|
/* No cache, so nothing to do. */
|
|
break;
|
|
case 8: /* MMU TLB control. */
|
|
switch (op2) {
|
|
case 0: /* Invalidate all. */
|
|
tlb_flush(env, 0);
|
|
break;
|
|
case 1: /* Invalidate single TLB entry. */
|
|
#if 0
|
|
/* ??? This is wrong for large pages and sections. */
|
|
/* As an ugly hack to make linux work we always flush a 4K
|
|
pages. */
|
|
val &= 0xfffff000;
|
|
tlb_flush_page(env, val);
|
|
tlb_flush_page(env, val + 0x400);
|
|
tlb_flush_page(env, val + 0x800);
|
|
tlb_flush_page(env, val + 0xc00);
|
|
#else
|
|
tlb_flush(env, 1);
|
|
#endif
|
|
break;
|
|
default:
|
|
goto bad_reg;
|
|
}
|
|
break;
|
|
case 9:
|
|
if (arm_feature(env, ARM_FEATURE_OMAPCP))
|
|
break;
|
|
switch (crm) {
|
|
case 0: /* Cache lockdown. */
|
|
switch (op2) {
|
|
case 0:
|
|
env->cp15.c9_data = val;
|
|
break;
|
|
case 1:
|
|
env->cp15.c9_insn = val;
|
|
break;
|
|
default:
|
|
goto bad_reg;
|
|
}
|
|
break;
|
|
case 1: /* TCM memory region registers. */
|
|
/* Not implemented. */
|
|
goto bad_reg;
|
|
default:
|
|
goto bad_reg;
|
|
}
|
|
break;
|
|
case 10: /* MMU TLB lockdown. */
|
|
/* ??? TLB lockdown not implemented. */
|
|
break;
|
|
case 12: /* Reserved. */
|
|
goto bad_reg;
|
|
case 13: /* Process ID. */
|
|
switch (op2) {
|
|
case 0:
|
|
/* Unlike real hardware the qemu TLB uses virtual addresses,
|
|
not modified virtual addresses, so this causes a TLB flush.
|
|
*/
|
|
if (env->cp15.c13_fcse != val)
|
|
tlb_flush(env, 1);
|
|
env->cp15.c13_fcse = val;
|
|
break;
|
|
case 1:
|
|
/* This changes the ASID, so do a TLB flush. */
|
|
if (env->cp15.c13_context != val
|
|
&& !arm_feature(env, ARM_FEATURE_MPU))
|
|
tlb_flush(env, 0);
|
|
env->cp15.c13_context = val;
|
|
break;
|
|
default:
|
|
goto bad_reg;
|
|
}
|
|
break;
|
|
case 14: /* Reserved. */
|
|
goto bad_reg;
|
|
case 15: /* Implementation specific. */
|
|
if (arm_feature(env, ARM_FEATURE_XSCALE)) {
|
|
if (op2 == 0 && crm == 1) {
|
|
if (env->cp15.c15_cpar != (val & 0x3fff)) {
|
|
/* Changes cp0 to cp13 behavior, so needs a TB flush. */
|
|
tb_flush(env);
|
|
env->cp15.c15_cpar = val & 0x3fff;
|
|
}
|
|
break;
|
|
}
|
|
goto bad_reg;
|
|
}
|
|
if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
|
|
switch (crm) {
|
|
case 0:
|
|
break;
|
|
case 1: /* Set TI925T configuration. */
|
|
env->cp15.c15_ticonfig = val & 0xe7;
|
|
env->cp15.c0_cpuid = (val & (1 << 5)) ? /* OS_TYPE bit */
|
|
ARM_CPUID_TI915T : ARM_CPUID_TI925T;
|
|
break;
|
|
case 2: /* Set I_max. */
|
|
env->cp15.c15_i_max = val;
|
|
break;
|
|
case 3: /* Set I_min. */
|
|
env->cp15.c15_i_min = val;
|
|
break;
|
|
case 4: /* Set thread-ID. */
|
|
env->cp15.c15_threadid = val & 0xffff;
|
|
break;
|
|
case 8: /* Wait-for-interrupt (deprecated). */
|
|
cpu_interrupt(env, CPU_INTERRUPT_HALT);
|
|
break;
|
|
default:
|
|
goto bad_reg;
|
|
}
|
|
}
|
|
break;
|
|
}
|
|
return;
|
|
bad_reg:
|
|
/* ??? For debugging only. Should raise illegal instruction exception. */
|
|
cpu_abort(env, "Unimplemented cp15 register write\n");
|
|
}
|
|
|
|
uint32_t helper_get_cp15(CPUState *env, uint32_t insn)
|
|
{
|
|
uint32_t op2;
|
|
uint32_t crm;
|
|
|
|
op2 = (insn >> 5) & 7;
|
|
crm = insn & 0xf;
|
|
switch ((insn >> 16) & 0xf) {
|
|
case 0: /* ID codes. */
|
|
switch (op2) {
|
|
default: /* Device ID. */
|
|
return env->cp15.c0_cpuid;
|
|
case 1: /* Cache Type. */
|
|
return env->cp15.c0_cachetype;
|
|
case 2: /* TCM status. */
|
|
if (arm_feature(env, ARM_FEATURE_XSCALE))
|
|
goto bad_reg;
|
|
return 0;
|
|
}
|
|
case 1: /* System configuration. */
|
|
if (arm_feature(env, ARM_FEATURE_OMAPCP))
|
|
op2 = 0;
|
|
switch (op2) {
|
|
case 0: /* Control register. */
|
|
return env->cp15.c1_sys;
|
|
case 1: /* Auxiliary control register. */
|
|
if (arm_feature(env, ARM_FEATURE_AUXCR))
|
|
return 1;
|
|
if (arm_feature(env, ARM_FEATURE_XSCALE))
|
|
return env->cp15.c1_xscaleauxcr;
|
|
goto bad_reg;
|
|
case 2: /* Coprocessor access register. */
|
|
if (arm_feature(env, ARM_FEATURE_XSCALE))
|
|
goto bad_reg;
|
|
return env->cp15.c1_coproc;
|
|
default:
|
|
goto bad_reg;
|
|
}
|
|
case 2: /* MMU Page table control / MPU cache control. */
|
|
if (arm_feature(env, ARM_FEATURE_MPU)) {
|
|
switch (op2) {
|
|
case 0:
|
|
return env->cp15.c2_data;
|
|
break;
|
|
case 1:
|
|
return env->cp15.c2_insn;
|
|
break;
|
|
default:
|
|
goto bad_reg;
|
|
}
|
|
} else {
|
|
return env->cp15.c2_base;
|
|
}
|
|
case 3: /* MMU Domain access control / MPU write buffer control. */
|
|
return env->cp15.c3;
|
|
case 4: /* Reserved. */
|
|
goto bad_reg;
|
|
case 5: /* MMU Fault status / MPU access permission. */
|
|
if (arm_feature(env, ARM_FEATURE_OMAPCP))
|
|
op2 = 0;
|
|
switch (op2) {
|
|
case 0:
|
|
if (arm_feature(env, ARM_FEATURE_MPU))
|
|
return simple_mpu_ap_bits(env->cp15.c5_data);
|
|
return env->cp15.c5_data;
|
|
case 1:
|
|
if (arm_feature(env, ARM_FEATURE_MPU))
|
|
return simple_mpu_ap_bits(env->cp15.c5_data);
|
|
return env->cp15.c5_insn;
|
|
case 2:
|
|
if (!arm_feature(env, ARM_FEATURE_MPU))
|
|
goto bad_reg;
|
|
return env->cp15.c5_data;
|
|
case 3:
|
|
if (!arm_feature(env, ARM_FEATURE_MPU))
|
|
goto bad_reg;
|
|
return env->cp15.c5_insn;
|
|
default:
|
|
goto bad_reg;
|
|
}
|
|
case 6: /* MMU Fault address / MPU base/size. */
|
|
if (arm_feature(env, ARM_FEATURE_MPU)) {
|
|
int n;
|
|
n = (insn & 0xf);
|
|
if (n >= 8)
|
|
goto bad_reg;
|
|
return env->cp15.c6_region[n];
|
|
} else {
|
|
if (arm_feature(env, ARM_FEATURE_OMAPCP))
|
|
op2 = 0;
|
|
switch (op2) {
|
|
case 0:
|
|
return env->cp15.c6_data;
|
|
case 1:
|
|
/* Arm9 doesn't have an IFAR, but implementing it anyway
|
|
shouldn't do any harm. */
|
|
return env->cp15.c6_insn;
|
|
default:
|
|
goto bad_reg;
|
|
}
|
|
}
|
|
case 7: /* Cache control. */
|
|
/* ??? This is for test, clean and invaidate operations that set the
|
|
Z flag. We can't represent N = Z = 1, so it also clears
|
|
the N flag. Oh well. */
|
|
env->NZF = 0;
|
|
return 0;
|
|
case 8: /* MMU TLB control. */
|
|
goto bad_reg;
|
|
case 9: /* Cache lockdown. */
|
|
if (arm_feature(env, ARM_FEATURE_OMAPCP))
|
|
return 0;
|
|
switch (op2) {
|
|
case 0:
|
|
return env->cp15.c9_data;
|
|
case 1:
|
|
return env->cp15.c9_insn;
|
|
default:
|
|
goto bad_reg;
|
|
}
|
|
case 10: /* MMU TLB lockdown. */
|
|
/* ??? TLB lockdown not implemented. */
|
|
return 0;
|
|
case 11: /* TCM DMA control. */
|
|
case 12: /* Reserved. */
|
|
goto bad_reg;
|
|
case 13: /* Process ID. */
|
|
switch (op2) {
|
|
case 0:
|
|
return env->cp15.c13_fcse;
|
|
case 1:
|
|
return env->cp15.c13_context;
|
|
default:
|
|
goto bad_reg;
|
|
}
|
|
case 14: /* Reserved. */
|
|
goto bad_reg;
|
|
case 15: /* Implementation specific. */
|
|
if (arm_feature(env, ARM_FEATURE_XSCALE)) {
|
|
if (op2 == 0 && crm == 1)
|
|
return env->cp15.c15_cpar;
|
|
|
|
goto bad_reg;
|
|
}
|
|
if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
|
|
switch (crm) {
|
|
case 0:
|
|
return 0;
|
|
case 1: /* Read TI925T configuration. */
|
|
return env->cp15.c15_ticonfig;
|
|
case 2: /* Read I_max. */
|
|
return env->cp15.c15_i_max;
|
|
case 3: /* Read I_min. */
|
|
return env->cp15.c15_i_min;
|
|
case 4: /* Read thread-ID. */
|
|
return env->cp15.c15_threadid;
|
|
case 8: /* TI925T_status */
|
|
return 0;
|
|
}
|
|
goto bad_reg;
|
|
}
|
|
return 0;
|
|
}
|
|
bad_reg:
|
|
/* ??? For debugging only. Should raise illegal instruction exception. */
|
|
cpu_abort(env, "Unimplemented cp15 register read\n");
|
|
return 0;
|
|
}
|
|
|
|
void cpu_arm_set_cp_io(CPUARMState *env, int cpnum,
|
|
ARMReadCPFunc *cp_read, ARMWriteCPFunc *cp_write,
|
|
void *opaque)
|
|
{
|
|
if (cpnum < 0 || cpnum > 14) {
|
|
cpu_abort(env, "Bad coprocessor number: %i\n", cpnum);
|
|
return;
|
|
}
|
|
|
|
env->cp[cpnum].cp_read = cp_read;
|
|
env->cp[cpnum].cp_write = cp_write;
|
|
env->cp[cpnum].opaque = opaque;
|
|
}
|
|
|
|
#endif
|