Ivan Klokov 270629024d

disas/riscv Fix ctzw disassemble ...

Due to typo in opcode list, ctzw is disassembled as clzw instruction.

Signed-off-by: Ivan Klokov <ivan.klokov@syntacore.com>
Fixes: 02c1b569a15b ("disas/riscv: Add Zb[abcs] instructions")
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20230217151459.54649-1-ivan.klokov@syntacore.com>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>

2023-03-05 12:43:38 -08:00

..

alpha.c

…

capstone.c

disas: use result of ->read_memory_func

2022-10-06 11:53:40 +01:00

cris.c

…

hexagon.c

Hexagon (disas/hexagon.c) fix memory leak for early exit cases

2021-08-12 09:06:05 -05:00

hppa.c

disas/: fix some comment spelling errors

2020-09-17 20:40:08 +02:00

m68k.c

disas/: fix some comment spelling errors

2020-09-17 20:40:08 +02:00

meson.build

mips: Always include nanomips disassembler

2023-01-13 16:22:53 +01:00

microblaze.c

…

mips.c

disas/mips: Fix branch displacement for BEQZC and BNEZC

2022-10-31 11:32:07 +01:00

nanomips.c

disas/nanomips: Tidy read for 48-bit opcodes

2022-11-08 01:04:25 +01:00

nios2.c

disas/nios2: Simplify endianess conversion

2021-10-22 18:07:30 +02:00

riscv.c

disas/riscv Fix ctzw disassemble

2023-03-05 12:43:38 -08:00

sh4.c

disas/sh4: Add missing fallthrough annotations

2020-07-13 11:40:52 +02:00

sparc.c

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xtensa.c

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