883f2c591f
The 'hwaddr' type is defined in "exec/hwaddr.h" as:
hwaddr is the type of a physical address
(its size can be different from 'target_ulong').
All definitions use the 'HWADDR_' prefix, except TARGET_FMT_plx:
$ fgrep define include/exec/hwaddr.h
#define HWADDR_H
#define HWADDR_BITS 64
#define HWADDR_MAX UINT64_MAX
#define TARGET_FMT_plx "%016" PRIx64
^^^^^^
#define HWADDR_PRId PRId64
#define HWADDR_PRIi PRIi64
#define HWADDR_PRIo PRIo64
#define HWADDR_PRIu PRIu64
#define HWADDR_PRIx PRIx64
#define HWADDR_PRIX PRIX64
Since hwaddr's size can be *different* from target_ulong, it is
very confusing to read one of its format using the 'TARGET_FMT_'
prefix, normally used for the target_long / target_ulong types:
$ fgrep TARGET_FMT_ include/exec/cpu-defs.h
#define TARGET_FMT_lx "%08x"
#define TARGET_FMT_ld "%d"
#define TARGET_FMT_lu "%u"
#define TARGET_FMT_lx "%016" PRIx64
#define TARGET_FMT_ld "%" PRId64
#define TARGET_FMT_lu "%" PRIu64
Apparently this format was missed during commit a8170e5e97
("Rename target_phys_addr_t to hwaddr"), so complete it by
doing a bulk-rename with:
$ sed -i -e s/TARGET_FMT_plx/HWADDR_FMT_plx/g $(git grep -l TARGET_FMT_plx)
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20230110212947.34557-1-philmd@linaro.org>
[thuth: Fix some warnings from checkpatch.pl along the way]
Signed-off-by: Thomas Huth <thuth@redhat.com>
270 lines
6.2 KiB
C
270 lines
6.2 KiB
C
/*
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* PXA270-based Intel Mainstone platforms.
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* FPGA driver
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*
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* Copyright (c) 2007 by Armin Kuster <akuster@kama-aina.net> or
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* <akuster@mvista.com>
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*
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* This code is licensed under the GNU GPL v2.
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*
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* Contributions after 2012-01-13 are licensed under the terms of the
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* GNU GPL, version 2 or (at your option) any later version.
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*/
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#include "qemu/osdep.h"
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#include "hw/irq.h"
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#include "hw/sysbus.h"
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#include "migration/vmstate.h"
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#include "qemu/module.h"
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#include "qom/object.h"
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/* Mainstone FPGA for extern irqs */
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#define FPGA_GPIO_PIN 0
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#define MST_NUM_IRQS 16
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#define MST_LEDDAT1 0x10
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#define MST_LEDDAT2 0x14
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#define MST_LEDCTRL 0x40
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#define MST_GPSWR 0x60
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#define MST_MSCWR1 0x80
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#define MST_MSCWR2 0x84
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#define MST_MSCWR3 0x88
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#define MST_MSCRD 0x90
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#define MST_INTMSKENA 0xc0
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#define MST_INTSETCLR 0xd0
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#define MST_PCMCIA0 0xe0
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#define MST_PCMCIA1 0xe4
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#define MST_PCMCIAx_READY (1 << 10)
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#define MST_PCMCIAx_nCD (1 << 5)
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#define MST_PCMCIA_CD0_IRQ 9
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#define MST_PCMCIA_CD1_IRQ 13
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#define TYPE_MAINSTONE_FPGA "mainstone-fpga"
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OBJECT_DECLARE_SIMPLE_TYPE(mst_irq_state, MAINSTONE_FPGA)
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struct mst_irq_state {
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SysBusDevice parent_obj;
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MemoryRegion iomem;
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qemu_irq parent;
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uint32_t prev_level;
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uint32_t leddat1;
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uint32_t leddat2;
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uint32_t ledctrl;
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uint32_t gpswr;
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uint32_t mscwr1;
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uint32_t mscwr2;
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uint32_t mscwr3;
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uint32_t mscrd;
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uint32_t intmskena;
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uint32_t intsetclr;
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uint32_t pcmcia0;
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uint32_t pcmcia1;
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};
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static void
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mst_fpga_set_irq(void *opaque, int irq, int level)
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{
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mst_irq_state *s = (mst_irq_state *)opaque;
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uint32_t oldint = s->intsetclr & s->intmskena;
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if (level)
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s->prev_level |= 1u << irq;
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else
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s->prev_level &= ~(1u << irq);
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switch(irq) {
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case MST_PCMCIA_CD0_IRQ:
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if (level)
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s->pcmcia0 &= ~MST_PCMCIAx_nCD;
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else
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s->pcmcia0 |= MST_PCMCIAx_nCD;
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break;
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case MST_PCMCIA_CD1_IRQ:
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if (level)
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s->pcmcia1 &= ~MST_PCMCIAx_nCD;
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else
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s->pcmcia1 |= MST_PCMCIAx_nCD;
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break;
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}
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if ((s->intmskena & (1u << irq)) && level)
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s->intsetclr |= 1u << irq;
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if (oldint != (s->intsetclr & s->intmskena))
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qemu_set_irq(s->parent, s->intsetclr & s->intmskena);
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}
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static uint64_t
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mst_fpga_readb(void *opaque, hwaddr addr, unsigned size)
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{
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mst_irq_state *s = (mst_irq_state *) opaque;
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switch (addr) {
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case MST_LEDDAT1:
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return s->leddat1;
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case MST_LEDDAT2:
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return s->leddat2;
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case MST_LEDCTRL:
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return s->ledctrl;
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case MST_GPSWR:
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return s->gpswr;
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case MST_MSCWR1:
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return s->mscwr1;
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case MST_MSCWR2:
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return s->mscwr2;
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case MST_MSCWR3:
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return s->mscwr3;
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case MST_MSCRD:
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return s->mscrd;
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case MST_INTMSKENA:
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return s->intmskena;
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case MST_INTSETCLR:
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return s->intsetclr;
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case MST_PCMCIA0:
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return s->pcmcia0;
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case MST_PCMCIA1:
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return s->pcmcia1;
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default:
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printf("Mainstone - mst_fpga_readb: Bad register offset "
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"0x" HWADDR_FMT_plx "\n", addr);
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}
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return 0;
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}
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static void
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mst_fpga_writeb(void *opaque, hwaddr addr, uint64_t value,
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unsigned size)
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{
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mst_irq_state *s = (mst_irq_state *) opaque;
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value &= 0xffffffff;
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switch (addr) {
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case MST_LEDDAT1:
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s->leddat1 = value;
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break;
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case MST_LEDDAT2:
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s->leddat2 = value;
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break;
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case MST_LEDCTRL:
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s->ledctrl = value;
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break;
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case MST_GPSWR:
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s->gpswr = value;
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break;
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case MST_MSCWR1:
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s->mscwr1 = value;
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break;
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case MST_MSCWR2:
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s->mscwr2 = value;
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break;
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case MST_MSCWR3:
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s->mscwr3 = value;
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break;
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case MST_MSCRD:
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s->mscrd = value;
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break;
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case MST_INTMSKENA: /* Mask interrupt */
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s->intmskena = (value & 0xFEEFF);
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qemu_set_irq(s->parent, s->intsetclr & s->intmskena);
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break;
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case MST_INTSETCLR: /* clear or set interrupt */
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s->intsetclr = (value & 0xFEEFF);
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qemu_set_irq(s->parent, s->intsetclr & s->intmskena);
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break;
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/* For PCMCIAx allow the to change only power and reset */
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case MST_PCMCIA0:
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s->pcmcia0 = (value & 0x1f) | (s->pcmcia0 & ~0x1f);
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break;
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case MST_PCMCIA1:
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s->pcmcia1 = (value & 0x1f) | (s->pcmcia1 & ~0x1f);
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break;
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default:
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printf("Mainstone - mst_fpga_writeb: Bad register offset "
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"0x" HWADDR_FMT_plx "\n", addr);
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}
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}
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static const MemoryRegionOps mst_fpga_ops = {
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.read = mst_fpga_readb,
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.write = mst_fpga_writeb,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static int mst_fpga_post_load(void *opaque, int version_id)
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{
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mst_irq_state *s = (mst_irq_state *) opaque;
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qemu_set_irq(s->parent, s->intsetclr & s->intmskena);
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return 0;
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}
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static void mst_fpga_init(Object *obj)
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{
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DeviceState *dev = DEVICE(obj);
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mst_irq_state *s = MAINSTONE_FPGA(obj);
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SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
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s->pcmcia0 = MST_PCMCIAx_READY | MST_PCMCIAx_nCD;
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s->pcmcia1 = MST_PCMCIAx_READY | MST_PCMCIAx_nCD;
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sysbus_init_irq(sbd, &s->parent);
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/* alloc the external 16 irqs */
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qdev_init_gpio_in(dev, mst_fpga_set_irq, MST_NUM_IRQS);
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memory_region_init_io(&s->iomem, obj, &mst_fpga_ops, s,
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"fpga", 0x00100000);
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sysbus_init_mmio(sbd, &s->iomem);
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}
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static const VMStateDescription vmstate_mst_fpga_regs = {
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.name = "mainstone_fpga",
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.version_id = 0,
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.minimum_version_id = 0,
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.post_load = mst_fpga_post_load,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(prev_level, mst_irq_state),
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VMSTATE_UINT32(leddat1, mst_irq_state),
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VMSTATE_UINT32(leddat2, mst_irq_state),
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VMSTATE_UINT32(ledctrl, mst_irq_state),
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VMSTATE_UINT32(gpswr, mst_irq_state),
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VMSTATE_UINT32(mscwr1, mst_irq_state),
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VMSTATE_UINT32(mscwr2, mst_irq_state),
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VMSTATE_UINT32(mscwr3, mst_irq_state),
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VMSTATE_UINT32(mscrd, mst_irq_state),
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VMSTATE_UINT32(intmskena, mst_irq_state),
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VMSTATE_UINT32(intsetclr, mst_irq_state),
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VMSTATE_UINT32(pcmcia0, mst_irq_state),
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VMSTATE_UINT32(pcmcia1, mst_irq_state),
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VMSTATE_END_OF_LIST(),
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},
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};
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static void mst_fpga_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->desc = "Mainstone II FPGA";
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dc->vmsd = &vmstate_mst_fpga_regs;
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}
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static const TypeInfo mst_fpga_info = {
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.name = TYPE_MAINSTONE_FPGA,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(mst_irq_state),
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.instance_init = mst_fpga_init,
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.class_init = mst_fpga_class_init,
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};
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static void mst_fpga_register_types(void)
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{
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type_register_static(&mst_fpga_info);
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}
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type_init(mst_fpga_register_types)
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