38dd78c41e
Commit 7f4f0d9ea8 ("linux-user/arm: Implement __kernel_cmpxchg with host
atomics") switched to use qatomic_cmpxchg() to swap a word with the memory
content, but missed to endianess-swap the oldval and newval values when
emulating an armeb CPU, which expects words to be stored in big endian in
the guest memory.
The bug can be verified with qemu >= v7.0 on any little-endian host, when
starting the armeb binary of the upx program, which just hangs without
this patch.
Cc: qemu-stable@nongnu.org
Signed-off-by: Helge Deller <deller@gmx.de>
Reported-by: "Markus F.X.J. Oberhumer" <markus@oberhumer.com>
Reported-by: John Reiser <jreiser@BitWagon.com>
Closes: https://github.com/upx/upx/issues/687
Message-Id: <ZMQVnqY+F+5sTNFd@p100>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
543 lines
18 KiB
C
543 lines
18 KiB
C
/*
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* qemu user cpu loop
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*
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* Copyright (c) 2003-2008 Fabrice Bellard
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qemu.h"
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#include "user-internals.h"
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#include "elf.h"
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#include "cpu_loop-common.h"
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#include "signal-common.h"
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#include "semihosting/common-semi.h"
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#include "target/arm/syndrome.h"
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#define get_user_code_u32(x, gaddr, env) \
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({ abi_long __r = get_user_u32((x), (gaddr)); \
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if (!__r && bswap_code(arm_sctlr_b(env))) { \
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(x) = bswap32(x); \
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} \
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__r; \
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})
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#define get_user_code_u16(x, gaddr, env) \
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({ abi_long __r = get_user_u16((x), (gaddr)); \
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if (!__r && bswap_code(arm_sctlr_b(env))) { \
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(x) = bswap16(x); \
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} \
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__r; \
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})
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#define get_user_data_u32(x, gaddr, env) \
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({ abi_long __r = get_user_u32((x), (gaddr)); \
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if (!__r && arm_cpu_bswap_data(env)) { \
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(x) = bswap32(x); \
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} \
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__r; \
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})
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#define get_user_data_u16(x, gaddr, env) \
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({ abi_long __r = get_user_u16((x), (gaddr)); \
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if (!__r && arm_cpu_bswap_data(env)) { \
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(x) = bswap16(x); \
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} \
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__r; \
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})
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#define put_user_data_u32(x, gaddr, env) \
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({ typeof(x) __x = (x); \
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if (arm_cpu_bswap_data(env)) { \
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__x = bswap32(__x); \
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} \
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put_user_u32(__x, (gaddr)); \
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})
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#define put_user_data_u16(x, gaddr, env) \
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({ typeof(x) __x = (x); \
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if (arm_cpu_bswap_data(env)) { \
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__x = bswap16(__x); \
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} \
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put_user_u16(__x, (gaddr)); \
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})
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/*
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* Similar to code in accel/tcg/user-exec.c, but outside the execution loop.
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* Must be called with mmap_lock.
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* We get the PC of the entry address - which is as good as anything,
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* on a real kernel what you get depends on which mode it uses.
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*/
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static void *atomic_mmu_lookup(CPUArchState *env, uint32_t addr, int size)
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{
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int need_flags = PAGE_READ | PAGE_WRITE_ORG | PAGE_VALID;
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int page_flags;
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/* Enforce guest required alignment. */
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if (unlikely(addr & (size - 1))) {
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force_sig_fault(TARGET_SIGBUS, TARGET_BUS_ADRALN, addr);
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return NULL;
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}
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page_flags = page_get_flags(addr);
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if (unlikely((page_flags & need_flags) != need_flags)) {
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force_sig_fault(TARGET_SIGSEGV,
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page_flags & PAGE_VALID ?
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TARGET_SEGV_ACCERR : TARGET_SEGV_MAPERR, addr);
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return NULL;
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}
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return g2h(env_cpu(env), addr);
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}
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/*
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* See the Linux kernel's Documentation/arm/kernel_user_helpers.rst
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* Input:
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* r0 = oldval
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* r1 = newval
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* r2 = pointer to target value
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*
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* Output:
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* r0 = 0 if *ptr was changed, non-0 if no exchange happened
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* C set if *ptr was changed, clear if no exchange happened
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*/
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static void arm_kernel_cmpxchg32_helper(CPUARMState *env)
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{
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uint32_t oldval, newval, val, addr, cpsr, *host_addr;
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/* Swap if host != guest endianness, for the host cmpxchg below */
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oldval = tswap32(env->regs[0]);
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newval = tswap32(env->regs[1]);
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addr = env->regs[2];
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mmap_lock();
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host_addr = atomic_mmu_lookup(env, addr, 4);
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if (!host_addr) {
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mmap_unlock();
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return;
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}
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val = qatomic_cmpxchg__nocheck(host_addr, oldval, newval);
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mmap_unlock();
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cpsr = (val == oldval) * CPSR_C;
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cpsr_write(env, cpsr, CPSR_C, CPSRWriteByInstr);
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env->regs[0] = cpsr ? 0 : -1;
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}
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/*
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* See the Linux kernel's Documentation/arm/kernel_user_helpers.rst
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* Input:
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* r0 = pointer to oldval
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* r1 = pointer to newval
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* r2 = pointer to target value
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*
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* Output:
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* r0 = 0 if *ptr was changed, non-0 if no exchange happened
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* C set if *ptr was changed, clear if no exchange happened
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*
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* Note segv's in kernel helpers are a bit tricky, we can set the
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* data address sensibly but the PC address is just the entry point.
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*/
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static void arm_kernel_cmpxchg64_helper(CPUARMState *env)
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{
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uint64_t oldval, newval, val;
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uint32_t addr, cpsr;
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uint64_t *host_addr;
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addr = env->regs[0];
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if (get_user_u64(oldval, addr)) {
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goto segv;
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}
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addr = env->regs[1];
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if (get_user_u64(newval, addr)) {
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goto segv;
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}
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mmap_lock();
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addr = env->regs[2];
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host_addr = atomic_mmu_lookup(env, addr, 8);
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if (!host_addr) {
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mmap_unlock();
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return;
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}
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/* Swap if host != guest endianness, for the host cmpxchg below */
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oldval = tswap64(oldval);
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newval = tswap64(newval);
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#ifdef CONFIG_ATOMIC64
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val = qatomic_cmpxchg__nocheck(host_addr, oldval, newval);
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cpsr = (val == oldval) * CPSR_C;
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#else
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/*
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* This only works between threads, not between processes, but since
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* the host has no 64-bit cmpxchg, it is the best that we can do.
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*/
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start_exclusive();
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val = *host_addr;
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if (val == oldval) {
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*host_addr = newval;
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cpsr = CPSR_C;
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} else {
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cpsr = 0;
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}
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end_exclusive();
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#endif
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mmap_unlock();
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cpsr_write(env, cpsr, CPSR_C, CPSRWriteByInstr);
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env->regs[0] = cpsr ? 0 : -1;
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return;
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segv:
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force_sig_fault(TARGET_SIGSEGV,
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page_get_flags(addr) & PAGE_VALID ?
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TARGET_SEGV_ACCERR : TARGET_SEGV_MAPERR, addr);
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}
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/* Handle a jump to the kernel code page. */
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static int
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do_kernel_trap(CPUARMState *env)
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{
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uint32_t addr;
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switch (env->regs[15]) {
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case 0xffff0fa0: /* __kernel_memory_barrier */
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smp_mb();
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break;
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case 0xffff0fc0: /* __kernel_cmpxchg */
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arm_kernel_cmpxchg32_helper(env);
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break;
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case 0xffff0fe0: /* __kernel_get_tls */
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env->regs[0] = cpu_get_tls(env);
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break;
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case 0xffff0f60: /* __kernel_cmpxchg64 */
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arm_kernel_cmpxchg64_helper(env);
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break;
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default:
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return 1;
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}
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/* Jump back to the caller. */
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addr = env->regs[14];
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if (addr & 1) {
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env->thumb = true;
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addr &= ~1;
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}
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env->regs[15] = addr;
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return 0;
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}
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static bool insn_is_linux_bkpt(uint32_t opcode, bool is_thumb)
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{
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/*
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* Return true if this insn is one of the three magic UDF insns
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* which the kernel treats as breakpoint insns.
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*/
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if (!is_thumb) {
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return (opcode & 0x0fffffff) == 0x07f001f0;
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} else {
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/*
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* Note that we get the two halves of the 32-bit T32 insn
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* in the opposite order to the value the kernel uses in
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* its undef_hook struct.
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*/
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return ((opcode & 0xffff) == 0xde01) || (opcode == 0xa000f7f0);
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}
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}
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static bool emulate_arm_fpa11(CPUARMState *env, uint32_t opcode)
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{
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TaskState *ts = env_cpu(env)->opaque;
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int rc = EmulateAll(opcode, &ts->fpa, env);
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int raise, enabled;
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if (rc == 0) {
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/* Illegal instruction */
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return false;
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}
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if (rc > 0) {
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/* Everything ok. */
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env->regs[15] += 4;
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return true;
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}
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/* FP exception */
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rc = -rc;
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raise = 0;
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/* Translate softfloat flags to FPSR flags */
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if (rc & float_flag_invalid) {
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raise |= BIT_IOC;
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}
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if (rc & float_flag_divbyzero) {
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raise |= BIT_DZC;
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}
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if (rc & float_flag_overflow) {
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raise |= BIT_OFC;
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}
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if (rc & float_flag_underflow) {
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raise |= BIT_UFC;
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}
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if (rc & float_flag_inexact) {
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raise |= BIT_IXC;
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}
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/* Accumulate unenabled exceptions */
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enabled = ts->fpa.fpsr >> 16;
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ts->fpa.fpsr |= raise & ~enabled;
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if (raise & enabled) {
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/*
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* The kernel's nwfpe emulator does not pass a real si_code.
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* It merely uses send_sig(SIGFPE, current, 1), which results in
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* __send_signal() filling out SI_KERNEL with pid and uid 0 (under
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* the "SEND_SIG_PRIV" case). That's what our force_sig() does.
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*/
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force_sig(TARGET_SIGFPE);
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} else {
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env->regs[15] += 4;
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}
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return true;
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}
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void cpu_loop(CPUARMState *env)
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{
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CPUState *cs = env_cpu(env);
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int trapnr, si_signo, si_code;
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unsigned int n, insn;
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abi_ulong ret;
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for(;;) {
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cpu_exec_start(cs);
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trapnr = cpu_exec(cs);
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cpu_exec_end(cs);
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process_queued_cpu_work(cs);
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switch(trapnr) {
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case EXCP_UDEF:
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case EXCP_NOCP:
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case EXCP_INVSTATE:
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{
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uint32_t opcode;
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/* we handle the FPU emulation here, as Linux */
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/* we get the opcode */
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/* FIXME - what to do if get_user() fails? */
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get_user_code_u32(opcode, env->regs[15], env);
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/*
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* The Linux kernel treats some UDF patterns specially
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* to use as breakpoints (instead of the architectural
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* bkpt insn). These should trigger a SIGTRAP rather
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* than SIGILL.
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*/
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if (insn_is_linux_bkpt(opcode, env->thumb)) {
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goto excp_debug;
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}
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if (!env->thumb && emulate_arm_fpa11(env, opcode)) {
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break;
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}
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force_sig_fault(TARGET_SIGILL, TARGET_ILL_ILLOPN,
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env->regs[15]);
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}
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break;
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case EXCP_SWI:
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{
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env->eabi = true;
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/* system call */
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if (env->thumb) {
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/* Thumb is always EABI style with syscall number in r7 */
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n = env->regs[7];
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} else {
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/*
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* Equivalent of kernel CONFIG_OABI_COMPAT: read the
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* Arm SVC insn to extract the immediate, which is the
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* syscall number in OABI.
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*/
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/* FIXME - what to do if get_user() fails? */
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get_user_code_u32(insn, env->regs[15] - 4, env);
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n = insn & 0xffffff;
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if (n == 0) {
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/* zero immediate: EABI, syscall number in r7 */
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n = env->regs[7];
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} else {
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/*
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* This XOR matches the kernel code: an immediate
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* in the valid range (0x900000 .. 0x9fffff) is
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* converted into the correct EABI-style syscall
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* number; invalid immediates end up as values
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* > 0xfffff and are handled below as out-of-range.
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*/
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n ^= ARM_SYSCALL_BASE;
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env->eabi = false;
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}
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}
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if (n > ARM_NR_BASE) {
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switch (n) {
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case ARM_NR_cacheflush:
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/* nop */
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break;
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case ARM_NR_set_tls:
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cpu_set_tls(env, env->regs[0]);
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env->regs[0] = 0;
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break;
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case ARM_NR_breakpoint:
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env->regs[15] -= env->thumb ? 2 : 4;
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goto excp_debug;
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case ARM_NR_get_tls:
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env->regs[0] = cpu_get_tls(env);
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break;
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default:
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if (n < 0xf0800) {
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/*
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* Syscalls 0xf0000..0xf07ff (or 0x9f0000..
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* 0x9f07ff in OABI numbering) are defined
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* to return -ENOSYS rather than raising
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* SIGILL. Note that we have already
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* removed the 0x900000 prefix.
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*/
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qemu_log_mask(LOG_UNIMP,
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"qemu: Unsupported ARM syscall: 0x%x\n",
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n);
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env->regs[0] = -TARGET_ENOSYS;
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} else {
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/*
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* Otherwise SIGILL. This includes any SWI with
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* immediate not originally 0x9fxxxx, because
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* of the earlier XOR.
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* Like the real kernel, we report the addr of the
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* SWI in the siginfo si_addr but leave the PC
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* pointing at the insn after the SWI.
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*/
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abi_ulong faultaddr = env->regs[15];
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faultaddr -= env->thumb ? 2 : 4;
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force_sig_fault(TARGET_SIGILL, TARGET_ILL_ILLTRP,
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faultaddr);
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}
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break;
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}
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} else {
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ret = do_syscall(env,
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n,
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env->regs[0],
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env->regs[1],
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env->regs[2],
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env->regs[3],
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env->regs[4],
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env->regs[5],
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0, 0);
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if (ret == -QEMU_ERESTARTSYS) {
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env->regs[15] -= env->thumb ? 2 : 4;
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} else if (ret != -QEMU_ESIGRETURN) {
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env->regs[0] = ret;
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}
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}
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}
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break;
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case EXCP_SEMIHOST:
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do_common_semihosting(cs);
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env->regs[15] += env->thumb ? 2 : 4;
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break;
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case EXCP_INTERRUPT:
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/* just indicate that signals should be handled asap */
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break;
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case EXCP_PREFETCH_ABORT:
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case EXCP_DATA_ABORT:
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/* For user-only we don't set TTBCR_EAE, so look at the FSR. */
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switch (env->exception.fsr & 0x1f) {
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case 0x1: /* Alignment */
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si_signo = TARGET_SIGBUS;
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si_code = TARGET_BUS_ADRALN;
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break;
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case 0x3: /* Access flag fault, level 1 */
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case 0x6: /* Access flag fault, level 2 */
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case 0x9: /* Domain fault, level 1 */
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case 0xb: /* Domain fault, level 2 */
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case 0xd: /* Permission fault, level 1 */
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case 0xf: /* Permission fault, level 2 */
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si_signo = TARGET_SIGSEGV;
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si_code = TARGET_SEGV_ACCERR;
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break;
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case 0x5: /* Translation fault, level 1 */
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case 0x7: /* Translation fault, level 2 */
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si_signo = TARGET_SIGSEGV;
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si_code = TARGET_SEGV_MAPERR;
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break;
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default:
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g_assert_not_reached();
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}
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force_sig_fault(si_signo, si_code, env->exception.vaddress);
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break;
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case EXCP_DEBUG:
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case EXCP_BKPT:
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excp_debug:
|
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force_sig_fault(TARGET_SIGTRAP, TARGET_TRAP_BRKPT, env->regs[15]);
|
|
break;
|
|
case EXCP_KERNEL_TRAP:
|
|
if (do_kernel_trap(env))
|
|
goto error;
|
|
break;
|
|
case EXCP_YIELD:
|
|
/* nothing to do here for user-mode, just resume guest code */
|
|
break;
|
|
case EXCP_ATOMIC:
|
|
cpu_exec_step_atomic(cs);
|
|
break;
|
|
default:
|
|
error:
|
|
EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
|
|
abort();
|
|
}
|
|
process_pending_signals(env);
|
|
}
|
|
}
|
|
|
|
void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs)
|
|
{
|
|
CPUState *cpu = env_cpu(env);
|
|
TaskState *ts = cpu->opaque;
|
|
struct image_info *info = ts->info;
|
|
int i;
|
|
|
|
cpsr_write(env, regs->uregs[16], CPSR_USER | CPSR_EXEC,
|
|
CPSRWriteByInstr);
|
|
for(i = 0; i < 16; i++) {
|
|
env->regs[i] = regs->uregs[i];
|
|
}
|
|
#if TARGET_BIG_ENDIAN
|
|
/* Enable BE8. */
|
|
if (EF_ARM_EABI_VERSION(info->elf_flags) >= EF_ARM_EABI_VER4
|
|
&& (info->elf_flags & EF_ARM_BE8)) {
|
|
env->uncached_cpsr |= CPSR_E;
|
|
env->cp15.sctlr_el[1] |= SCTLR_E0E;
|
|
} else {
|
|
env->cp15.sctlr_el[1] |= SCTLR_B;
|
|
}
|
|
arm_rebuild_hflags(env);
|
|
#endif
|
|
|
|
ts->stack_base = info->start_stack;
|
|
ts->heap_base = info->brk;
|
|
/* This will be filled in on the first SYS_HEAPINFO call. */
|
|
ts->heap_limit = 0;
|
|
}
|