1038 lines
29 KiB
C
1038 lines
29 KiB
C
/*
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* QEMU PCI bus manager
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*
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* Copyright (c) 2004 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw.h"
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#include "pci.h"
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#include "monitor.h"
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#include "net.h"
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#include "sysemu.h"
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//#define DEBUG_PCI
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struct PCIBus {
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BusState qbus;
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int bus_num;
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int devfn_min;
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pci_set_irq_fn set_irq;
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pci_map_irq_fn map_irq;
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uint32_t config_reg; /* XXX: suppress */
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/* low level pic */
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SetIRQFunc *low_set_irq;
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qemu_irq *irq_opaque;
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PCIDevice *devices[256];
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PCIDevice *parent_dev;
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PCIBus *next;
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/* The bus IRQ state is the logical OR of the connected devices.
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Keep a count of the number of devices with raised IRQs. */
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int nirq;
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int *irq_count;
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};
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static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent);
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static struct BusInfo pci_bus_info = {
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.name = "PCI",
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.size = sizeof(PCIBus),
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.print_dev = pcibus_dev_print,
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};
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static void pci_update_mappings(PCIDevice *d);
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static void pci_set_irq(void *opaque, int irq_num, int level);
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target_phys_addr_t pci_mem_base;
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static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET;
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static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU;
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static PCIBus *first_bus;
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static void pcibus_save(QEMUFile *f, void *opaque)
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{
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PCIBus *bus = (PCIBus *)opaque;
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int i;
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qemu_put_be32(f, bus->nirq);
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for (i = 0; i < bus->nirq; i++)
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qemu_put_be32(f, bus->irq_count[i]);
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}
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static int pcibus_load(QEMUFile *f, void *opaque, int version_id)
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{
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PCIBus *bus = (PCIBus *)opaque;
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int i, nirq;
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if (version_id != 1)
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return -EINVAL;
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nirq = qemu_get_be32(f);
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if (bus->nirq != nirq) {
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fprintf(stderr, "pcibus_load: nirq mismatch: src=%d dst=%d\n",
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nirq, bus->nirq);
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return -EINVAL;
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}
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for (i = 0; i < nirq; i++)
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bus->irq_count[i] = qemu_get_be32(f);
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return 0;
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}
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static void pci_bus_reset(void *opaque)
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{
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PCIBus *bus = (PCIBus *)opaque;
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int i;
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for (i = 0; i < bus->nirq; i++) {
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bus->irq_count[i] = 0;
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}
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for (i = 0; i < 256; i++) {
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if (bus->devices[i])
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memset(bus->devices[i]->irq_state, 0,
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sizeof(bus->devices[i]->irq_state));
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}
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}
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PCIBus *pci_register_bus(DeviceState *parent, const char *name,
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pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
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qemu_irq *pic, int devfn_min, int nirq)
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{
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PCIBus *bus;
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static int nbus = 0;
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bus = FROM_QBUS(PCIBus, qbus_create(&pci_bus_info, parent, name));
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bus->set_irq = set_irq;
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bus->map_irq = map_irq;
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bus->irq_opaque = pic;
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bus->devfn_min = devfn_min;
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bus->nirq = nirq;
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bus->irq_count = qemu_mallocz(nirq * sizeof(bus->irq_count[0]));
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bus->next = first_bus;
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first_bus = bus;
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register_savevm("PCIBUS", nbus++, 1, pcibus_save, pcibus_load, bus);
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qemu_register_reset(pci_bus_reset, bus);
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return bus;
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}
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static PCIBus *pci_register_secondary_bus(PCIDevice *dev, pci_map_irq_fn map_irq)
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{
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PCIBus *bus;
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bus = qemu_mallocz(sizeof(PCIBus));
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bus->map_irq = map_irq;
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bus->parent_dev = dev;
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bus->next = dev->bus->next;
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dev->bus->next = bus;
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return bus;
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}
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int pci_bus_num(PCIBus *s)
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{
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return s->bus_num;
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}
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void pci_device_save(PCIDevice *s, QEMUFile *f)
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{
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int i;
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qemu_put_be32(f, 2); /* PCI device version */
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qemu_put_buffer(f, s->config, 256);
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for (i = 0; i < 4; i++)
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qemu_put_be32(f, s->irq_state[i]);
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}
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int pci_device_load(PCIDevice *s, QEMUFile *f)
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{
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uint8_t config[PCI_CONFIG_SPACE_SIZE];
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uint32_t version_id;
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int i;
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version_id = qemu_get_be32(f);
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if (version_id > 2)
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return -EINVAL;
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qemu_get_buffer(f, config, sizeof config);
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for (i = 0; i < sizeof config; ++i)
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if ((config[i] ^ s->config[i]) & s->cmask[i] & ~s->wmask[i])
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return -EINVAL;
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memcpy(s->config, config, sizeof config);
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pci_update_mappings(s);
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if (version_id >= 2)
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for (i = 0; i < 4; i ++)
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s->irq_state[i] = qemu_get_be32(f);
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return 0;
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}
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static int pci_set_default_subsystem_id(PCIDevice *pci_dev)
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{
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uint16_t *id;
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id = (void*)(&pci_dev->config[PCI_SUBVENDOR_ID]);
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id[0] = cpu_to_le16(pci_default_sub_vendor_id);
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id[1] = cpu_to_le16(pci_default_sub_device_id);
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return 0;
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}
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/*
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* Parse [[<domain>:]<bus>:]<slot>, return -1 on error
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*/
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static int pci_parse_devaddr(const char *addr, int *domp, int *busp, unsigned *slotp)
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{
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const char *p;
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char *e;
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unsigned long val;
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unsigned long dom = 0, bus = 0;
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unsigned slot = 0;
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p = addr;
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val = strtoul(p, &e, 16);
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if (e == p)
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return -1;
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if (*e == ':') {
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bus = val;
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p = e + 1;
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val = strtoul(p, &e, 16);
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if (e == p)
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return -1;
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if (*e == ':') {
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dom = bus;
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bus = val;
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p = e + 1;
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val = strtoul(p, &e, 16);
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if (e == p)
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return -1;
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}
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}
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if (dom > 0xffff || bus > 0xff || val > 0x1f)
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return -1;
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slot = val;
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if (*e)
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return -1;
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/* Note: QEMU doesn't implement domains other than 0 */
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if (dom != 0 || pci_find_bus(bus) == NULL)
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return -1;
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*domp = dom;
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*busp = bus;
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*slotp = slot;
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return 0;
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}
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int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp,
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unsigned *slotp)
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{
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/* strip legacy tag */
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if (!strncmp(addr, "pci_addr=", 9)) {
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addr += 9;
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}
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if (pci_parse_devaddr(addr, domp, busp, slotp)) {
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monitor_printf(mon, "Invalid pci address\n");
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return -1;
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}
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return 0;
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}
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static PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr)
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{
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int dom, bus;
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unsigned slot;
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if (!devaddr) {
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*devfnp = -1;
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return pci_find_bus(0);
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}
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if (pci_parse_devaddr(devaddr, &dom, &bus, &slot) < 0) {
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return NULL;
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}
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*devfnp = slot << 3;
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return pci_find_bus(bus);
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}
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static void pci_init_cmask(PCIDevice *dev)
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{
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pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff);
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pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff);
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dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST;
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dev->cmask[PCI_REVISION_ID] = 0xff;
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dev->cmask[PCI_CLASS_PROG] = 0xff;
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pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff);
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dev->cmask[PCI_HEADER_TYPE] = 0xff;
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dev->cmask[PCI_CAPABILITY_LIST] = 0xff;
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}
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static void pci_init_wmask(PCIDevice *dev)
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{
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int i;
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dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff;
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dev->wmask[PCI_INTERRUPT_LINE] = 0xff;
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dev->wmask[PCI_COMMAND] = PCI_COMMAND_IO | PCI_COMMAND_MEMORY
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| PCI_COMMAND_MASTER;
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for (i = PCI_CONFIG_HEADER_SIZE; i < PCI_CONFIG_SPACE_SIZE; ++i)
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dev->wmask[i] = 0xff;
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}
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/* -1 for devfn means auto assign */
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static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus,
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const char *name, int devfn,
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PCIConfigReadFunc *config_read,
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PCIConfigWriteFunc *config_write)
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{
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if (devfn < 0) {
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for(devfn = bus->devfn_min ; devfn < 256; devfn += 8) {
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if (!bus->devices[devfn])
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goto found;
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}
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return NULL;
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found: ;
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} else if (bus->devices[devfn]) {
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return NULL;
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}
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pci_dev->bus = bus;
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pci_dev->devfn = devfn;
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pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
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memset(pci_dev->irq_state, 0, sizeof(pci_dev->irq_state));
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pci_set_default_subsystem_id(pci_dev);
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pci_init_cmask(pci_dev);
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pci_init_wmask(pci_dev);
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if (!config_read)
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config_read = pci_default_read_config;
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if (!config_write)
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config_write = pci_default_write_config;
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pci_dev->config_read = config_read;
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pci_dev->config_write = config_write;
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bus->devices[devfn] = pci_dev;
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pci_dev->irq = qemu_allocate_irqs(pci_set_irq, pci_dev, 4);
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return pci_dev;
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}
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PCIDevice *pci_register_device(PCIBus *bus, const char *name,
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int instance_size, int devfn,
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PCIConfigReadFunc *config_read,
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PCIConfigWriteFunc *config_write)
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{
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PCIDevice *pci_dev;
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pci_dev = qemu_mallocz(instance_size);
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pci_dev = do_pci_register_device(pci_dev, bus, name, devfn,
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config_read, config_write);
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return pci_dev;
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}
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static target_phys_addr_t pci_to_cpu_addr(target_phys_addr_t addr)
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{
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return addr + pci_mem_base;
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}
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static void pci_unregister_io_regions(PCIDevice *pci_dev)
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{
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PCIIORegion *r;
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int i;
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for(i = 0; i < PCI_NUM_REGIONS; i++) {
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r = &pci_dev->io_regions[i];
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if (!r->size || r->addr == -1)
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continue;
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if (r->type == PCI_ADDRESS_SPACE_IO) {
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isa_unassign_ioport(r->addr, r->size);
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} else {
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cpu_register_physical_memory(pci_to_cpu_addr(r->addr),
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r->size,
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IO_MEM_UNASSIGNED);
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}
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}
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}
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int pci_unregister_device(PCIDevice *pci_dev)
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{
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int ret = 0;
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if (pci_dev->unregister)
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ret = pci_dev->unregister(pci_dev);
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if (ret)
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return ret;
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pci_unregister_io_regions(pci_dev);
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qemu_free_irqs(pci_dev->irq);
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pci_dev->bus->devices[pci_dev->devfn] = NULL;
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qdev_free(&pci_dev->qdev);
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return 0;
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}
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void pci_register_bar(PCIDevice *pci_dev, int region_num,
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uint32_t size, int type,
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PCIMapIORegionFunc *map_func)
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{
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PCIIORegion *r;
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uint32_t addr;
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uint32_t wmask;
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if ((unsigned int)region_num >= PCI_NUM_REGIONS)
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return;
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if (size & (size-1)) {
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fprintf(stderr, "ERROR: PCI region size must be pow2 "
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"type=0x%x, size=0x%x\n", type, size);
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exit(1);
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}
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r = &pci_dev->io_regions[region_num];
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r->addr = -1;
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r->size = size;
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r->type = type;
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r->map_func = map_func;
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wmask = ~(size - 1);
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if (region_num == PCI_ROM_SLOT) {
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addr = 0x30;
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/* ROM enable bit is writeable */
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wmask |= 1;
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} else {
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addr = 0x10 + region_num * 4;
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}
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*(uint32_t *)(pci_dev->config + addr) = cpu_to_le32(type);
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*(uint32_t *)(pci_dev->wmask + addr) = cpu_to_le32(wmask);
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*(uint32_t *)(pci_dev->cmask + addr) = 0xffffffff;
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}
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static void pci_update_mappings(PCIDevice *d)
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{
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PCIIORegion *r;
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int cmd, i;
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uint32_t last_addr, new_addr, config_ofs;
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cmd = le16_to_cpu(*(uint16_t *)(d->config + PCI_COMMAND));
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for(i = 0; i < PCI_NUM_REGIONS; i++) {
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r = &d->io_regions[i];
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if (i == PCI_ROM_SLOT) {
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config_ofs = 0x30;
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} else {
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config_ofs = 0x10 + i * 4;
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}
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if (r->size != 0) {
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if (r->type & PCI_ADDRESS_SPACE_IO) {
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if (cmd & PCI_COMMAND_IO) {
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new_addr = le32_to_cpu(*(uint32_t *)(d->config +
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config_ofs));
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new_addr = new_addr & ~(r->size - 1);
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last_addr = new_addr + r->size - 1;
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/* NOTE: we have only 64K ioports on PC */
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if (last_addr <= new_addr || new_addr == 0 ||
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last_addr >= 0x10000) {
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new_addr = -1;
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}
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} else {
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new_addr = -1;
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}
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} else {
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if (cmd & PCI_COMMAND_MEMORY) {
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new_addr = le32_to_cpu(*(uint32_t *)(d->config +
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config_ofs));
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/* the ROM slot has a specific enable bit */
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if (i == PCI_ROM_SLOT && !(new_addr & 1))
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goto no_mem_map;
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new_addr = new_addr & ~(r->size - 1);
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last_addr = new_addr + r->size - 1;
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/* NOTE: we do not support wrapping */
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/* XXX: as we cannot support really dynamic
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mappings, we handle specific values as invalid
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mappings. */
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if (last_addr <= new_addr || new_addr == 0 ||
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last_addr == -1) {
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new_addr = -1;
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}
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} else {
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no_mem_map:
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new_addr = -1;
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}
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}
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/* now do the real mapping */
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if (new_addr != r->addr) {
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if (r->addr != -1) {
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if (r->type & PCI_ADDRESS_SPACE_IO) {
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int class;
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/* NOTE: specific hack for IDE in PC case:
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only one byte must be mapped. */
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class = d->config[0x0a] | (d->config[0x0b] << 8);
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if (class == 0x0101 && r->size == 4) {
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isa_unassign_ioport(r->addr + 2, 1);
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} else {
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isa_unassign_ioport(r->addr, r->size);
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}
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} else {
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cpu_register_physical_memory(pci_to_cpu_addr(r->addr),
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r->size,
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IO_MEM_UNASSIGNED);
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qemu_unregister_coalesced_mmio(r->addr, r->size);
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}
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}
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r->addr = new_addr;
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if (r->addr != -1) {
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r->map_func(d, i, r->addr, r->size, r->type);
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}
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}
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}
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}
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}
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|
|
uint32_t pci_default_read_config(PCIDevice *d,
|
|
uint32_t address, int len)
|
|
{
|
|
uint32_t val;
|
|
|
|
switch(len) {
|
|
default:
|
|
case 4:
|
|
if (address <= 0xfc) {
|
|
val = le32_to_cpu(*(uint32_t *)(d->config + address));
|
|
break;
|
|
}
|
|
/* fall through */
|
|
case 2:
|
|
if (address <= 0xfe) {
|
|
val = le16_to_cpu(*(uint16_t *)(d->config + address));
|
|
break;
|
|
}
|
|
/* fall through */
|
|
case 1:
|
|
val = d->config[address];
|
|
break;
|
|
}
|
|
return val;
|
|
}
|
|
|
|
void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l)
|
|
{
|
|
uint8_t orig[PCI_CONFIG_SPACE_SIZE];
|
|
int i;
|
|
|
|
/* not efficient, but simple */
|
|
memcpy(orig, d->config, PCI_CONFIG_SPACE_SIZE);
|
|
for(i = 0; i < l && addr < PCI_CONFIG_SPACE_SIZE; val >>= 8, ++i, ++addr) {
|
|
uint8_t wmask = d->wmask[addr];
|
|
d->config[addr] = (d->config[addr] & ~wmask) | (val & wmask);
|
|
}
|
|
if (memcmp(orig + PCI_BASE_ADDRESS_0, d->config + PCI_BASE_ADDRESS_0, 24)
|
|
|| ((orig[PCI_COMMAND] ^ d->config[PCI_COMMAND])
|
|
& (PCI_COMMAND_MEMORY | PCI_COMMAND_IO)))
|
|
pci_update_mappings(d);
|
|
}
|
|
|
|
void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len)
|
|
{
|
|
PCIBus *s = opaque;
|
|
PCIDevice *pci_dev;
|
|
int config_addr, bus_num;
|
|
|
|
#if defined(DEBUG_PCI) && 0
|
|
printf("pci_data_write: addr=%08x val=%08x len=%d\n",
|
|
addr, val, len);
|
|
#endif
|
|
bus_num = (addr >> 16) & 0xff;
|
|
while (s && s->bus_num != bus_num)
|
|
s = s->next;
|
|
if (!s)
|
|
return;
|
|
pci_dev = s->devices[(addr >> 8) & 0xff];
|
|
if (!pci_dev)
|
|
return;
|
|
config_addr = addr & 0xff;
|
|
#if defined(DEBUG_PCI)
|
|
printf("pci_config_write: %s: addr=%02x val=%08x len=%d\n",
|
|
pci_dev->name, config_addr, val, len);
|
|
#endif
|
|
pci_dev->config_write(pci_dev, config_addr, val, len);
|
|
}
|
|
|
|
uint32_t pci_data_read(void *opaque, uint32_t addr, int len)
|
|
{
|
|
PCIBus *s = opaque;
|
|
PCIDevice *pci_dev;
|
|
int config_addr, bus_num;
|
|
uint32_t val;
|
|
|
|
bus_num = (addr >> 16) & 0xff;
|
|
while (s && s->bus_num != bus_num)
|
|
s= s->next;
|
|
if (!s)
|
|
goto fail;
|
|
pci_dev = s->devices[(addr >> 8) & 0xff];
|
|
if (!pci_dev) {
|
|
fail:
|
|
switch(len) {
|
|
case 1:
|
|
val = 0xff;
|
|
break;
|
|
case 2:
|
|
val = 0xffff;
|
|
break;
|
|
default:
|
|
case 4:
|
|
val = 0xffffffff;
|
|
break;
|
|
}
|
|
goto the_end;
|
|
}
|
|
config_addr = addr & 0xff;
|
|
val = pci_dev->config_read(pci_dev, config_addr, len);
|
|
#if defined(DEBUG_PCI)
|
|
printf("pci_config_read: %s: addr=%02x val=%08x len=%d\n",
|
|
pci_dev->name, config_addr, val, len);
|
|
#endif
|
|
the_end:
|
|
#if defined(DEBUG_PCI) && 0
|
|
printf("pci_data_read: addr=%08x val=%08x len=%d\n",
|
|
addr, val, len);
|
|
#endif
|
|
return val;
|
|
}
|
|
|
|
/***********************************************************/
|
|
/* generic PCI irq support */
|
|
|
|
/* 0 <= irq_num <= 3. level must be 0 or 1 */
|
|
static void pci_set_irq(void *opaque, int irq_num, int level)
|
|
{
|
|
PCIDevice *pci_dev = (PCIDevice *)opaque;
|
|
PCIBus *bus;
|
|
int change;
|
|
|
|
change = level - pci_dev->irq_state[irq_num];
|
|
if (!change)
|
|
return;
|
|
|
|
pci_dev->irq_state[irq_num] = level;
|
|
for (;;) {
|
|
bus = pci_dev->bus;
|
|
irq_num = bus->map_irq(pci_dev, irq_num);
|
|
if (bus->set_irq)
|
|
break;
|
|
pci_dev = bus->parent_dev;
|
|
}
|
|
bus->irq_count[irq_num] += change;
|
|
bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);
|
|
}
|
|
|
|
/***********************************************************/
|
|
/* monitor info on PCI */
|
|
|
|
typedef struct {
|
|
uint16_t class;
|
|
const char *desc;
|
|
} pci_class_desc;
|
|
|
|
static const pci_class_desc pci_class_descriptions[] =
|
|
{
|
|
{ 0x0100, "SCSI controller"},
|
|
{ 0x0101, "IDE controller"},
|
|
{ 0x0102, "Floppy controller"},
|
|
{ 0x0103, "IPI controller"},
|
|
{ 0x0104, "RAID controller"},
|
|
{ 0x0106, "SATA controller"},
|
|
{ 0x0107, "SAS controller"},
|
|
{ 0x0180, "Storage controller"},
|
|
{ 0x0200, "Ethernet controller"},
|
|
{ 0x0201, "Token Ring controller"},
|
|
{ 0x0202, "FDDI controller"},
|
|
{ 0x0203, "ATM controller"},
|
|
{ 0x0280, "Network controller"},
|
|
{ 0x0300, "VGA controller"},
|
|
{ 0x0301, "XGA controller"},
|
|
{ 0x0302, "3D controller"},
|
|
{ 0x0380, "Display controller"},
|
|
{ 0x0400, "Video controller"},
|
|
{ 0x0401, "Audio controller"},
|
|
{ 0x0402, "Phone"},
|
|
{ 0x0480, "Multimedia controller"},
|
|
{ 0x0500, "RAM controller"},
|
|
{ 0x0501, "Flash controller"},
|
|
{ 0x0580, "Memory controller"},
|
|
{ 0x0600, "Host bridge"},
|
|
{ 0x0601, "ISA bridge"},
|
|
{ 0x0602, "EISA bridge"},
|
|
{ 0x0603, "MC bridge"},
|
|
{ 0x0604, "PCI bridge"},
|
|
{ 0x0605, "PCMCIA bridge"},
|
|
{ 0x0606, "NUBUS bridge"},
|
|
{ 0x0607, "CARDBUS bridge"},
|
|
{ 0x0608, "RACEWAY bridge"},
|
|
{ 0x0680, "Bridge"},
|
|
{ 0x0c03, "USB controller"},
|
|
{ 0, NULL}
|
|
};
|
|
|
|
static void pci_info_device(PCIDevice *d)
|
|
{
|
|
Monitor *mon = cur_mon;
|
|
int i, class;
|
|
PCIIORegion *r;
|
|
const pci_class_desc *desc;
|
|
|
|
monitor_printf(mon, " Bus %2d, device %3d, function %d:\n",
|
|
d->bus->bus_num, d->devfn >> 3, d->devfn & 7);
|
|
class = le16_to_cpu(*((uint16_t *)(d->config + PCI_CLASS_DEVICE)));
|
|
monitor_printf(mon, " ");
|
|
desc = pci_class_descriptions;
|
|
while (desc->desc && class != desc->class)
|
|
desc++;
|
|
if (desc->desc) {
|
|
monitor_printf(mon, "%s", desc->desc);
|
|
} else {
|
|
monitor_printf(mon, "Class %04x", class);
|
|
}
|
|
monitor_printf(mon, ": PCI device %04x:%04x\n",
|
|
le16_to_cpu(*((uint16_t *)(d->config + PCI_VENDOR_ID))),
|
|
le16_to_cpu(*((uint16_t *)(d->config + PCI_DEVICE_ID))));
|
|
|
|
if (d->config[PCI_INTERRUPT_PIN] != 0) {
|
|
monitor_printf(mon, " IRQ %d.\n",
|
|
d->config[PCI_INTERRUPT_LINE]);
|
|
}
|
|
if (class == 0x0604) {
|
|
monitor_printf(mon, " BUS %d.\n", d->config[0x19]);
|
|
}
|
|
for(i = 0;i < PCI_NUM_REGIONS; i++) {
|
|
r = &d->io_regions[i];
|
|
if (r->size != 0) {
|
|
monitor_printf(mon, " BAR%d: ", i);
|
|
if (r->type & PCI_ADDRESS_SPACE_IO) {
|
|
monitor_printf(mon, "I/O at 0x%04x [0x%04x].\n",
|
|
r->addr, r->addr + r->size - 1);
|
|
} else {
|
|
monitor_printf(mon, "32 bit memory at 0x%08x [0x%08x].\n",
|
|
r->addr, r->addr + r->size - 1);
|
|
}
|
|
}
|
|
}
|
|
if (class == 0x0604 && d->config[0x19] != 0) {
|
|
pci_for_each_device(d->config[0x19], pci_info_device);
|
|
}
|
|
}
|
|
|
|
void pci_for_each_device(int bus_num, void (*fn)(PCIDevice *d))
|
|
{
|
|
PCIBus *bus = first_bus;
|
|
PCIDevice *d;
|
|
int devfn;
|
|
|
|
while (bus && bus->bus_num != bus_num)
|
|
bus = bus->next;
|
|
if (bus) {
|
|
for(devfn = 0; devfn < 256; devfn++) {
|
|
d = bus->devices[devfn];
|
|
if (d)
|
|
fn(d);
|
|
}
|
|
}
|
|
}
|
|
|
|
void pci_info(Monitor *mon)
|
|
{
|
|
pci_for_each_device(0, pci_info_device);
|
|
}
|
|
|
|
PCIDevice *pci_create(const char *name, const char *devaddr)
|
|
{
|
|
PCIBus *bus;
|
|
int devfn;
|
|
DeviceState *dev;
|
|
|
|
bus = pci_get_bus_devfn(&devfn, devaddr);
|
|
if (!bus) {
|
|
fprintf(stderr, "Invalid PCI device address %s for device %s\n",
|
|
devaddr, name);
|
|
exit(1);
|
|
}
|
|
|
|
dev = qdev_create(&bus->qbus, name);
|
|
qdev_set_prop_int(dev, "devfn", devfn);
|
|
return (PCIDevice *)dev;
|
|
}
|
|
|
|
static const char * const pci_nic_models[] = {
|
|
"ne2k_pci",
|
|
"i82551",
|
|
"i82557b",
|
|
"i82559er",
|
|
"rtl8139",
|
|
"e1000",
|
|
"pcnet",
|
|
"virtio",
|
|
NULL
|
|
};
|
|
|
|
static const char * const pci_nic_names[] = {
|
|
"ne2k_pci",
|
|
"i82551",
|
|
"i82557b",
|
|
"i82559er",
|
|
"rtl8139",
|
|
"e1000",
|
|
"pcnet",
|
|
"virtio-net-pci",
|
|
NULL
|
|
};
|
|
|
|
/* Initialize a PCI NIC. */
|
|
PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model,
|
|
const char *default_devaddr)
|
|
{
|
|
const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr;
|
|
PCIDevice *pci_dev;
|
|
DeviceState *dev;
|
|
int i;
|
|
|
|
qemu_check_nic_model_list(nd, pci_nic_models, default_model);
|
|
|
|
for (i = 0; pci_nic_models[i]; i++) {
|
|
if (strcmp(nd->model, pci_nic_models[i]) == 0) {
|
|
pci_dev = pci_create(pci_nic_names[i], devaddr);
|
|
dev = &pci_dev->qdev;
|
|
qdev_set_netdev(dev, nd);
|
|
qdev_init(dev);
|
|
nd->private = dev;
|
|
return pci_dev;
|
|
}
|
|
}
|
|
|
|
return NULL;
|
|
}
|
|
|
|
typedef struct {
|
|
PCIDevice dev;
|
|
PCIBus *bus;
|
|
} PCIBridge;
|
|
|
|
static void pci_bridge_write_config(PCIDevice *d,
|
|
uint32_t address, uint32_t val, int len)
|
|
{
|
|
PCIBridge *s = (PCIBridge *)d;
|
|
|
|
pci_default_write_config(d, address, val, len);
|
|
s->bus->bus_num = d->config[PCI_SECONDARY_BUS];
|
|
}
|
|
|
|
PCIBus *pci_find_bus(int bus_num)
|
|
{
|
|
PCIBus *bus = first_bus;
|
|
|
|
while (bus && bus->bus_num != bus_num)
|
|
bus = bus->next;
|
|
|
|
return bus;
|
|
}
|
|
|
|
PCIDevice *pci_find_device(int bus_num, int slot, int function)
|
|
{
|
|
PCIBus *bus = pci_find_bus(bus_num);
|
|
|
|
if (!bus)
|
|
return NULL;
|
|
|
|
return bus->devices[PCI_DEVFN(slot, function)];
|
|
}
|
|
|
|
PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint16_t vid, uint16_t did,
|
|
pci_map_irq_fn map_irq, const char *name)
|
|
{
|
|
PCIBridge *s;
|
|
s = (PCIBridge *)pci_register_device(bus, name, sizeof(PCIBridge),
|
|
devfn, NULL, pci_bridge_write_config);
|
|
|
|
pci_config_set_vendor_id(s->dev.config, vid);
|
|
pci_config_set_device_id(s->dev.config, did);
|
|
|
|
s->dev.config[0x04] = 0x06; // command = bus master, pci mem
|
|
s->dev.config[0x05] = 0x00;
|
|
s->dev.config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error
|
|
s->dev.config[0x07] = 0x00; // status = fast devsel
|
|
s->dev.config[0x08] = 0x00; // revision
|
|
s->dev.config[0x09] = 0x00; // programming i/f
|
|
pci_config_set_class(s->dev.config, PCI_CLASS_BRIDGE_PCI);
|
|
s->dev.config[0x0D] = 0x10; // latency_timer
|
|
s->dev.config[PCI_HEADER_TYPE] =
|
|
PCI_HEADER_TYPE_MULTI_FUNCTION | PCI_HEADER_TYPE_BRIDGE; // header_type
|
|
s->dev.config[0x1E] = 0xa0; // secondary status
|
|
|
|
s->bus = pci_register_secondary_bus(&s->dev, map_irq);
|
|
return s->bus;
|
|
}
|
|
|
|
static void pci_qdev_init(DeviceState *qdev, DeviceInfo *base)
|
|
{
|
|
PCIDevice *pci_dev = (PCIDevice *)qdev;
|
|
PCIDeviceInfo *info = container_of(base, PCIDeviceInfo, qdev);
|
|
PCIBus *bus;
|
|
int devfn;
|
|
|
|
bus = FROM_QBUS(PCIBus, qdev_get_parent_bus(qdev));
|
|
devfn = qdev_get_prop_int(qdev, "devfn", -1);
|
|
pci_dev = do_pci_register_device(pci_dev, bus, base->name, devfn,
|
|
info->config_read, info->config_write);
|
|
assert(pci_dev);
|
|
info->init(pci_dev);
|
|
}
|
|
|
|
void pci_qdev_register(PCIDeviceInfo *info)
|
|
{
|
|
info->qdev.init = pci_qdev_init;
|
|
info->qdev.bus_info = &pci_bus_info;
|
|
qdev_register(&info->qdev);
|
|
}
|
|
|
|
void pci_qdev_register_many(PCIDeviceInfo *info)
|
|
{
|
|
while (info->qdev.name) {
|
|
pci_qdev_register(info);
|
|
info++;
|
|
}
|
|
}
|
|
|
|
PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name)
|
|
{
|
|
DeviceState *dev;
|
|
|
|
dev = qdev_create(&bus->qbus, name);
|
|
qdev_set_prop_int(dev, "devfn", devfn);
|
|
qdev_init(dev);
|
|
|
|
return (PCIDevice *)dev;
|
|
}
|
|
|
|
static int pci_find_space(PCIDevice *pdev, uint8_t size)
|
|
{
|
|
int offset = PCI_CONFIG_HEADER_SIZE;
|
|
int i;
|
|
for (i = PCI_CONFIG_HEADER_SIZE; i < PCI_CONFIG_SPACE_SIZE; ++i)
|
|
if (pdev->used[i])
|
|
offset = i + 1;
|
|
else if (i - offset + 1 == size)
|
|
return offset;
|
|
return 0;
|
|
}
|
|
|
|
static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id,
|
|
uint8_t *prev_p)
|
|
{
|
|
uint8_t next, prev;
|
|
|
|
if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST))
|
|
return 0;
|
|
|
|
for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]);
|
|
prev = next + PCI_CAP_LIST_NEXT)
|
|
if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id)
|
|
break;
|
|
|
|
if (prev_p)
|
|
*prev_p = prev;
|
|
return next;
|
|
}
|
|
|
|
/* Reserve space and add capability to the linked list in pci config space */
|
|
int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
|
|
{
|
|
uint8_t offset = pci_find_space(pdev, size);
|
|
uint8_t *config = pdev->config + offset;
|
|
if (!offset)
|
|
return -ENOSPC;
|
|
config[PCI_CAP_LIST_ID] = cap_id;
|
|
config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST];
|
|
pdev->config[PCI_CAPABILITY_LIST] = offset;
|
|
pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST;
|
|
memset(pdev->used + offset, 0xFF, size);
|
|
/* Make capability read-only by default */
|
|
memset(pdev->wmask + offset, 0, size);
|
|
/* Check capability by default */
|
|
memset(pdev->cmask + offset, 0xFF, size);
|
|
return offset;
|
|
}
|
|
|
|
/* Unlink capability from the pci config space. */
|
|
void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
|
|
{
|
|
uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev);
|
|
if (!offset)
|
|
return;
|
|
pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT];
|
|
/* Make capability writeable again */
|
|
memset(pdev->wmask + offset, 0xff, size);
|
|
/* Clear cmask as device-specific registers can't be checked */
|
|
memset(pdev->cmask + offset, 0, size);
|
|
memset(pdev->used + offset, 0, size);
|
|
|
|
if (!pdev->config[PCI_CAPABILITY_LIST])
|
|
pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST;
|
|
}
|
|
|
|
/* Reserve space for capability at a known offset (to call after load). */
|
|
void pci_reserve_capability(PCIDevice *pdev, uint8_t offset, uint8_t size)
|
|
{
|
|
memset(pdev->used + offset, 0xff, size);
|
|
}
|
|
|
|
uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id)
|
|
{
|
|
return pci_find_capability_list(pdev, cap_id, NULL);
|
|
}
|
|
|
|
static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent)
|
|
{
|
|
PCIDevice *d = (PCIDevice *)dev;
|
|
const pci_class_desc *desc;
|
|
char ctxt[64];
|
|
PCIIORegion *r;
|
|
int i, class;
|
|
|
|
class = le16_to_cpu(*((uint16_t *)(d->config + PCI_CLASS_DEVICE)));
|
|
desc = pci_class_descriptions;
|
|
while (desc->desc && class != desc->class)
|
|
desc++;
|
|
if (desc->desc) {
|
|
snprintf(ctxt, sizeof(ctxt), "%s", desc->desc);
|
|
} else {
|
|
snprintf(ctxt, sizeof(ctxt), "Class %04x", class);
|
|
}
|
|
|
|
monitor_printf(mon, "%*sclass %s, addr %02x:%02x.%x, "
|
|
"pci id %04x:%04x (sub %04x:%04x)\n",
|
|
indent, "", ctxt,
|
|
d->bus->bus_num, d->devfn >> 3, d->devfn & 7,
|
|
le16_to_cpu(*((uint16_t *)(d->config + PCI_VENDOR_ID))),
|
|
le16_to_cpu(*((uint16_t *)(d->config + PCI_DEVICE_ID))),
|
|
le16_to_cpu(*((uint16_t *)(d->config + PCI_SUBSYSTEM_VENDOR_ID))),
|
|
le16_to_cpu(*((uint16_t *)(d->config + PCI_SUBSYSTEM_ID))));
|
|
for (i = 0; i < PCI_NUM_REGIONS; i++) {
|
|
r = &d->io_regions[i];
|
|
if (!r->size)
|
|
continue;
|
|
monitor_printf(mon, "%*sbar %d: %s at 0x%x [0x%x]\n", indent, "",
|
|
i, r->type & PCI_ADDRESS_SPACE_IO ? "i/o" : "mem",
|
|
r->addr, r->addr + r->size - 1);
|
|
}
|
|
}
|