226263fb5c
To enable hotplugging of a newly created pcie-pci-bridge, we need to tell firmware (e.g. SeaBIOS) to reserve additional buses or IO/MEM/PREF space for pcie-root-port. Additional bus reservation allows us to hotplug pcie-pci-bridge into this root port. The number of buses and IO/MEM/PREF space to reserve are provided to the device via a corresponding property, and to the firmware via new PCI capability. The properties' default values are -1 to keep default behavior unchanged. Signed-off-by: Aleksandr Bezzubikov <zuban32s@gmail.com> Reviewed-by: Marcel Apfelbaum <marcel@redhat.com> Tested-by: Marcel Apfelbaum <marcel@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
149 lines
4.1 KiB
C
149 lines
4.1 KiB
C
/*
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* Generic PCI Express Root Port emulation
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*
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* Copyright (C) 2017 Red Hat Inc
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*
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* Authors:
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* Marcel Apfelbaum <marcel@redhat.com>
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "hw/pci/msix.h"
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#include "hw/pci/pcie_port.h"
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#define TYPE_GEN_PCIE_ROOT_PORT "pcie-root-port"
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#define GEN_PCIE_ROOT_PORT(obj) \
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OBJECT_CHECK(GenPCIERootPort, (obj), TYPE_GEN_PCIE_ROOT_PORT)
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#define GEN_PCIE_ROOT_PORT_AER_OFFSET 0x100
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#define GEN_PCIE_ROOT_PORT_MSIX_NR_VECTOR 1
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typedef struct GenPCIERootPort {
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/*< private >*/
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PCIESlot parent_obj;
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/*< public >*/
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bool migrate_msix;
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/* additional resources to reserve on firmware init */
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uint32_t bus_reserve;
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uint64_t io_reserve;
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uint64_t mem_reserve;
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uint64_t pref32_reserve;
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uint64_t pref64_reserve;
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} GenPCIERootPort;
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static uint8_t gen_rp_aer_vector(const PCIDevice *d)
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{
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return 0;
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}
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static int gen_rp_interrupts_init(PCIDevice *d, Error **errp)
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{
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int rc;
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rc = msix_init_exclusive_bar(d, GEN_PCIE_ROOT_PORT_MSIX_NR_VECTOR, 0, errp);
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if (rc < 0) {
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assert(rc == -ENOTSUP);
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} else {
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msix_vector_use(d, 0);
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}
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return rc;
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}
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static void gen_rp_interrupts_uninit(PCIDevice *d)
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{
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msix_uninit_exclusive_bar(d);
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}
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static bool gen_rp_test_migrate_msix(void *opaque, int version_id)
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{
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GenPCIERootPort *rp = opaque;
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return rp->migrate_msix;
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}
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static void gen_rp_realize(DeviceState *dev, Error **errp)
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{
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PCIDevice *d = PCI_DEVICE(dev);
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GenPCIERootPort *grp = GEN_PCIE_ROOT_PORT(d);
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PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(d);
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rpc->parent_realize(dev, errp);
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int rc = pci_bridge_qemu_reserve_cap_init(d, 0, grp->bus_reserve,
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grp->io_reserve, grp->mem_reserve, grp->pref32_reserve,
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grp->pref64_reserve, errp);
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if (rc < 0) {
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rpc->parent_class.exit(d);
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return;
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}
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}
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static const VMStateDescription vmstate_rp_dev = {
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.name = "pcie-root-port",
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.version_id = 1,
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.minimum_version_id = 1,
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.post_load = pcie_cap_slot_post_load,
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.fields = (VMStateField[]) {
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VMSTATE_PCI_DEVICE(parent_obj.parent_obj.parent_obj, PCIESlot),
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VMSTATE_STRUCT(parent_obj.parent_obj.parent_obj.exp.aer_log,
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PCIESlot, 0, vmstate_pcie_aer_log, PCIEAERLog),
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VMSTATE_MSIX_TEST(parent_obj.parent_obj.parent_obj.parent_obj,
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GenPCIERootPort,
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gen_rp_test_migrate_msix),
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VMSTATE_END_OF_LIST()
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}
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};
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static Property gen_rp_props[] = {
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DEFINE_PROP_BOOL("x-migrate-msix", GenPCIERootPort, migrate_msix, true),
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DEFINE_PROP_UINT32("bus-reserve", GenPCIERootPort, bus_reserve, -1),
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DEFINE_PROP_SIZE("io-reserve", GenPCIERootPort, io_reserve, -1),
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DEFINE_PROP_SIZE("mem-reserve", GenPCIERootPort, mem_reserve, -1),
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DEFINE_PROP_SIZE("pref32-reserve", GenPCIERootPort, pref32_reserve, -1),
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DEFINE_PROP_SIZE("pref64-reserve", GenPCIERootPort, pref64_reserve, -1),
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DEFINE_PROP_END_OF_LIST()
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};
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static void gen_rp_dev_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
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PCIERootPortClass *rpc = PCIE_ROOT_PORT_CLASS(klass);
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k->vendor_id = PCI_VENDOR_ID_REDHAT;
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k->device_id = PCI_DEVICE_ID_REDHAT_PCIE_RP;
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dc->desc = "PCI Express Root Port";
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dc->vmsd = &vmstate_rp_dev;
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dc->props = gen_rp_props;
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rpc->parent_realize = dc->realize;
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dc->realize = gen_rp_realize;
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rpc->aer_vector = gen_rp_aer_vector;
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rpc->interrupts_init = gen_rp_interrupts_init;
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rpc->interrupts_uninit = gen_rp_interrupts_uninit;
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rpc->aer_offset = GEN_PCIE_ROOT_PORT_AER_OFFSET;
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}
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static const TypeInfo gen_rp_dev_info = {
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.name = TYPE_GEN_PCIE_ROOT_PORT,
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.parent = TYPE_PCIE_ROOT_PORT,
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.instance_size = sizeof(GenPCIERootPort),
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.class_init = gen_rp_dev_class_init,
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};
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static void gen_rp_register_types(void)
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{
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type_register_static(&gen_rp_dev_info);
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}
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type_init(gen_rp_register_types)
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