qemu-e2k/target/openrisc
Richard Henderson 3a7be55465 decodetree: Remove "insn" argument from trans_* expanders
This allows trans_* expanders to be shared between decoders
for 32 and 16-bit insns, by not tying the expander to the
size of the insn that produced it.

This change requires adjusting the two existing users to match.

Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-10-31 16:48:54 +00:00
..
Makefile.objs target/openrisc: Merge mmu_helper.c into mmu.c 2018-07-03 00:05:28 +09:00
cpu.c linux-user: Implement signals for openrisc 2018-07-03 22:40:33 +09:00
cpu.h target/openrisc: Reorg tlb lookup 2018-07-03 22:40:33 +09:00
disas.c decodetree: Remove "insn" argument from trans_* expanders 2018-10-31 16:48:54 +00:00
exception.c
exception.h
exception_helper.c misc: remove duplicated includes 2017-12-18 17:07:02 +03:00
fpu_helper.c target-openrisc: Write back result before FPE exception 2018-05-14 14:35:02 -07:00
gdbstub.c target/openrisc: implement shadow registers 2017-05-04 09:39:01 +09:00
helper.h target/openrisc: Form the spr index from tcg 2018-07-03 00:05:28 +09:00
insns.decode target/openrisc: Convert dec_float 2018-05-14 14:55:29 -07:00
interrupt.c target/openrisc: Fix delay slot exception flag to match spec 2018-07-03 22:40:33 +09:00
interrupt_helper.c target/openrisc: Fix cpu_mmu_index 2018-07-03 00:05:28 +09:00
machine.c target/openrisc: Increase the TLB size 2018-07-03 00:05:28 +09:00
mmu.c target/openrisc: Reorg tlb lookup 2018-07-03 22:40:33 +09:00
sys_helper.c target/openrisc: Fix writes to interrupt mask register 2018-07-03 22:40:33 +09:00
translate.c decodetree: Remove "insn" argument from trans_* expanders 2018-10-31 16:48:54 +00:00