1b4a5a20da
infrastructure for vhost-vdpa shadow work piix south bridge rework reconnect for vhost-user-scsi dummy ACPI QTG DSM for cxl tests, cleanups, fixes all over the place Signed-off-by: Michael S. Tsirkin <mst@redhat.com> -----BEGIN PGP SIGNATURE----- iQFDBAABCAAtFiEEXQn9CHHI+FuUyooNKB8NuNKNVGkFAmU06PMPHG1zdEByZWRo YXQuY29tAAoJECgfDbjSjVRpNIsH/0DlKti86VZLJ6PbNqsnKxoK2gg05TbEhPZU pQ+RPDaCHpFBsLC5qsoMJwvaEQFe0e49ZFemw7bXRzBxgmbbNnZ9ArCIPqT+rvQd 7UBmyC+kacVyybZatq69aK2BHKFtiIRlT78d9Izgtjmp8V7oyKoz14Esh8wkE+FT ypHUa70Addi6alNm6BVkm7bxZxi0Wrmf3THqF8ViYvufzHKl7JR5e17fKWEG0BqV 9W7AeHMnzJ7jkTvBGUw7g5EbzFn7hPLTbO4G/VW97k0puS4WRX5aIMkVhUazsRIa zDOuXCCskUWuRapiCwY0E4g7cCaT8/JR6JjjBaTgkjJgvo5Y8Eg= =ILek -----END PGP SIGNATURE----- Merge tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu into staging virtio,pc,pci: features, cleanups infrastructure for vhost-vdpa shadow work piix south bridge rework reconnect for vhost-user-scsi dummy ACPI QTG DSM for cxl tests, cleanups, fixes all over the place Signed-off-by: Michael S. Tsirkin <mst@redhat.com> # -----BEGIN PGP SIGNATURE----- # # iQFDBAABCAAtFiEEXQn9CHHI+FuUyooNKB8NuNKNVGkFAmU06PMPHG1zdEByZWRo # YXQuY29tAAoJECgfDbjSjVRpNIsH/0DlKti86VZLJ6PbNqsnKxoK2gg05TbEhPZU # pQ+RPDaCHpFBsLC5qsoMJwvaEQFe0e49ZFemw7bXRzBxgmbbNnZ9ArCIPqT+rvQd # 7UBmyC+kacVyybZatq69aK2BHKFtiIRlT78d9Izgtjmp8V7oyKoz14Esh8wkE+FT # ypHUa70Addi6alNm6BVkm7bxZxi0Wrmf3THqF8ViYvufzHKl7JR5e17fKWEG0BqV # 9W7AeHMnzJ7jkTvBGUw7g5EbzFn7hPLTbO4G/VW97k0puS4WRX5aIMkVhUazsRIa # zDOuXCCskUWuRapiCwY0E4g7cCaT8/JR6JjjBaTgkjJgvo5Y8Eg= # =ILek # -----END PGP SIGNATURE----- # gpg: Signature made Sun 22 Oct 2023 02:18:43 PDT # gpg: using RSA key 5D09FD0871C8F85B94CA8A0D281F0DB8D28D5469 # gpg: issuer "mst@redhat.com" # gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" [full] # gpg: aka "Michael S. Tsirkin <mst@redhat.com>" [full] # Primary key fingerprint: 0270 606B 6F3C DF3D 0B17 0970 C350 3912 AFBE 8E67 # Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA 8A0D 281F 0DB8 D28D 5469 * tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu: (62 commits) intel-iommu: Report interrupt remapping faults, fix return value MAINTAINERS: Add include/hw/intc/i8259.h to the PC chip section vhost-user: Fix protocol feature bit conflict tests/acpi: Update DSDT.cxl with QTG DSM hw/cxl: Add QTG _DSM support for ACPI0017 device tests/acpi: Allow update of DSDT.cxl hw/i386/cxl: ensure maxram is greater than ram size for calculating cxl range vhost-user: fix lost reconnect vhost-user-scsi: start vhost when guest kicks vhost-user-scsi: support reconnect to backend vhost: move and rename the conn retry times vhost-user-common: send get_inflight_fd once hw/i386/pc_piix: Make PIIX4 south bridge usable in PC machine hw/isa/piix: Implement multi-process QEMU support also for PIIX4 hw/isa/piix: Resolve duplicate code regarding PCI interrupt wiring hw/isa/piix: Reuse PIIX3's PCI interrupt triggering in PIIX4 hw/isa/piix: Rename functions to be shared for PCI interrupt triggering hw/isa/piix: Reuse PIIX3 base class' realize method in PIIX4 hw/isa/piix: Share PIIX3's base class with PIIX4 hw/isa/piix: Harmonize names of reset control memory regions ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
1316 lines
41 KiB
C
1316 lines
41 KiB
C
/*
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* QEMU Malta board support
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*
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* Copyright (c) 2006 Aurelien Jarno
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "qemu/osdep.h"
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#include "qemu/units.h"
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#include "qemu/bitops.h"
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#include "qemu/datadir.h"
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#include "qemu/guest-random.h"
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#include "hw/clock.h"
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#include "hw/southbridge/piix.h"
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#include "hw/isa/superio.h"
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#include "hw/char/serial.h"
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#include "net/net.h"
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#include "hw/boards.h"
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#include "hw/i2c/smbus_eeprom.h"
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#include "hw/block/flash.h"
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#include "hw/mips/mips.h"
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#include "hw/mips/bootloader.h"
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#include "hw/pci/pci.h"
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#include "hw/pci/pci_bus.h"
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#include "qemu/log.h"
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#include "hw/mips/bios.h"
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#include "hw/ide/pci.h"
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#include "hw/irq.h"
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#include "hw/loader.h"
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#include "elf.h"
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#include "qom/object.h"
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#include "hw/sysbus.h" /* SysBusDevice */
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#include "qemu/host-utils.h"
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#include "sysemu/qtest.h"
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#include "sysemu/reset.h"
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#include "sysemu/runstate.h"
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#include "qapi/error.h"
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#include "qemu/error-report.h"
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#include "sysemu/kvm.h"
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#include "semihosting/semihost.h"
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#include "hw/mips/cps.h"
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#include "hw/qdev-clock.h"
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#include "target/mips/internal.h"
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#include "trace.h"
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#define ENVP_PADDR 0x2000
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#define ENVP_VADDR cpu_mips_phys_to_kseg0(NULL, ENVP_PADDR)
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#define ENVP_NB_ENTRIES 16
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#define ENVP_ENTRY_SIZE 256
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/* Hardware addresses */
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#define FLASH_ADDRESS 0x1e000000ULL
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#define FPGA_ADDRESS 0x1f000000ULL
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#define RESET_ADDRESS 0x1fc00000ULL
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#define FLASH_SIZE 0x400000
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#define PIIX4_PCI_DEVFN PCI_DEVFN(10, 0)
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typedef struct {
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MemoryRegion iomem;
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MemoryRegion iomem_lo; /* 0 - 0x900 */
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MemoryRegion iomem_hi; /* 0xa00 - 0x100000 */
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uint32_t leds;
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uint32_t brk;
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uint32_t gpout;
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uint32_t i2cin;
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uint32_t i2coe;
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uint32_t i2cout;
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uint32_t i2csel;
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CharBackend display;
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char display_text[9];
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SerialMM *uart;
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bool display_inited;
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} MaltaFPGAState;
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#define TYPE_MIPS_MALTA "mips-malta"
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OBJECT_DECLARE_SIMPLE_TYPE(MaltaState, MIPS_MALTA)
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struct MaltaState {
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SysBusDevice parent_obj;
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Clock *cpuclk;
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MIPSCPSState cps;
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};
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static struct _loaderparams {
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int ram_size, ram_low_size;
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const char *kernel_filename;
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const char *kernel_cmdline;
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const char *initrd_filename;
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} loaderparams;
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/* Malta FPGA */
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static void malta_fpga_update_display_leds(MaltaFPGAState *s)
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{
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char leds_text[9];
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int i;
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for (i = 7 ; i >= 0 ; i--) {
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if (s->leds & (1 << i)) {
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leds_text[i] = '#';
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} else {
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leds_text[i] = ' ';
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}
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}
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leds_text[8] = '\0';
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trace_malta_fpga_leds(leds_text);
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qemu_chr_fe_printf(&s->display, "\e[H\n\n|\e[32m%-8.8s\e[00m|\r\n",
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leds_text);
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}
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static void malta_fpga_update_display_ascii(MaltaFPGAState *s)
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{
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trace_malta_fpga_display(s->display_text);
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qemu_chr_fe_printf(&s->display, "\n\n\n\n|\e[31m%-8.8s\e[00m|",
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s->display_text);
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}
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/*
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* EEPROM 24C01 / 24C02 emulation.
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*
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* Emulation for serial EEPROMs:
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* 24C01 - 1024 bit (128 x 8)
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* 24C02 - 2048 bit (256 x 8)
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*
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* Typical device names include Microchip 24C02SC or SGS Thomson ST24C02.
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*/
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#if defined(DEBUG)
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# define logout(fmt, ...) \
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fprintf(stderr, "MALTA\t%-24s" fmt, __func__, ## __VA_ARGS__)
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#else
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# define logout(fmt, ...) ((void)0)
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#endif
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struct _eeprom24c0x_t {
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uint8_t tick;
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uint8_t address;
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uint8_t command;
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uint8_t ack;
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uint8_t scl;
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uint8_t sda;
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uint8_t data;
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/* uint16_t size; */
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uint8_t contents[256];
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};
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typedef struct _eeprom24c0x_t eeprom24c0x_t;
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static eeprom24c0x_t spd_eeprom = {
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.contents = {
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/* 00000000: */
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0x80, 0x08, 0xFF, 0x0D, 0x0A, 0xFF, 0x40, 0x00,
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/* 00000008: */
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0x01, 0x75, 0x54, 0x00, 0x82, 0x08, 0x00, 0x01,
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/* 00000010: */
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0x8F, 0x04, 0x02, 0x01, 0x01, 0x00, 0x00, 0x00,
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/* 00000018: */
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0x00, 0x00, 0x00, 0x14, 0x0F, 0x14, 0x2D, 0xFF,
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/* 00000020: */
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0x15, 0x08, 0x15, 0x08, 0x00, 0x00, 0x00, 0x00,
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/* 00000028: */
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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/* 00000030: */
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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/* 00000038: */
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x12, 0xD0,
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/* 00000040: */
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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/* 00000048: */
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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/* 00000050: */
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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/* 00000058: */
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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/* 00000060: */
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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/* 00000068: */
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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/* 00000070: */
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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/* 00000078: */
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x64, 0xF4,
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},
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};
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static void generate_eeprom_spd(uint8_t *eeprom, ram_addr_t ram_size)
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{
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enum sdram_type type;
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uint8_t *spd = spd_eeprom.contents;
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uint8_t nbanks = 0;
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uint16_t density = 0;
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int i;
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/* work in terms of MB */
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ram_size /= MiB;
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while ((ram_size >= 4) && (nbanks <= 2)) {
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int sz_log2 = MIN(31 - clz32(ram_size), 14);
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nbanks++;
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density |= 1 << (sz_log2 - 2);
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ram_size -= 1 << sz_log2;
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}
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/* split to 2 banks if possible */
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if ((nbanks == 1) && (density > 1)) {
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nbanks++;
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density >>= 1;
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}
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if (density & 0xff00) {
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density = (density & 0xe0) | ((density >> 8) & 0x1f);
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type = DDR2;
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} else if (!(density & 0x1f)) {
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type = DDR2;
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} else {
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type = SDR;
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}
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if (ram_size) {
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warn_report("SPD cannot represent final " RAM_ADDR_FMT "MB"
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" of SDRAM", ram_size);
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}
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/* fill in SPD memory information */
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spd[2] = type;
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spd[5] = nbanks;
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spd[31] = density;
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/* checksum */
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spd[63] = 0;
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for (i = 0; i < 63; i++) {
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spd[63] += spd[i];
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}
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/* copy for SMBUS */
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memcpy(eeprom, spd, sizeof(spd_eeprom.contents));
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}
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static void generate_eeprom_serial(uint8_t *eeprom)
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{
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int i, pos = 0;
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uint8_t mac[6] = { 0x00 };
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uint8_t sn[5] = { 0x01, 0x23, 0x45, 0x67, 0x89 };
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/* version */
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eeprom[pos++] = 0x01;
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/* count */
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eeprom[pos++] = 0x02;
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/* MAC address */
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eeprom[pos++] = 0x01; /* MAC */
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eeprom[pos++] = 0x06; /* length */
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memcpy(&eeprom[pos], mac, sizeof(mac));
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pos += sizeof(mac);
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/* serial number */
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eeprom[pos++] = 0x02; /* serial */
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eeprom[pos++] = 0x05; /* length */
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memcpy(&eeprom[pos], sn, sizeof(sn));
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pos += sizeof(sn);
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/* checksum */
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eeprom[pos] = 0;
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for (i = 0; i < pos; i++) {
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eeprom[pos] += eeprom[i];
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}
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}
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static uint8_t eeprom24c0x_read(eeprom24c0x_t *eeprom)
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{
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logout("%u: scl = %u, sda = %u, data = 0x%02x\n",
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eeprom->tick, eeprom->scl, eeprom->sda, eeprom->data);
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return eeprom->sda;
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}
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static void eeprom24c0x_write(eeprom24c0x_t *eeprom, int scl, int sda)
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{
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if (eeprom->scl && scl && (eeprom->sda != sda)) {
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logout("%u: scl = %u->%u, sda = %u->%u i2c %s\n",
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eeprom->tick, eeprom->scl, scl, eeprom->sda, sda,
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sda ? "stop" : "start");
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if (!sda) {
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eeprom->tick = 1;
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eeprom->command = 0;
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}
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} else if (eeprom->tick == 0 && !eeprom->ack) {
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/* Waiting for start. */
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logout("%u: scl = %u->%u, sda = %u->%u wait for i2c start\n",
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eeprom->tick, eeprom->scl, scl, eeprom->sda, sda);
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} else if (!eeprom->scl && scl) {
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logout("%u: scl = %u->%u, sda = %u->%u trigger bit\n",
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eeprom->tick, eeprom->scl, scl, eeprom->sda, sda);
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if (eeprom->ack) {
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logout("\ti2c ack bit = 0\n");
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sda = 0;
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eeprom->ack = 0;
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} else if (eeprom->sda == sda) {
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uint8_t bit = (sda != 0);
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logout("\ti2c bit = %d\n", bit);
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if (eeprom->tick < 9) {
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eeprom->command <<= 1;
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eeprom->command += bit;
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eeprom->tick++;
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if (eeprom->tick == 9) {
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logout("\tcommand 0x%04x, %s\n", eeprom->command,
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bit ? "read" : "write");
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eeprom->ack = 1;
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}
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} else if (eeprom->tick < 17) {
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if (eeprom->command & 1) {
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sda = ((eeprom->data & 0x80) != 0);
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}
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eeprom->address <<= 1;
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eeprom->address += bit;
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eeprom->tick++;
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eeprom->data <<= 1;
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if (eeprom->tick == 17) {
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eeprom->data = eeprom->contents[eeprom->address];
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logout("\taddress 0x%04x, data 0x%02x\n",
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eeprom->address, eeprom->data);
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eeprom->ack = 1;
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eeprom->tick = 0;
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}
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} else if (eeprom->tick >= 17) {
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sda = 0;
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}
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} else {
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logout("\tsda changed with raising scl\n");
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}
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} else {
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logout("%u: scl = %u->%u, sda = %u->%u\n", eeprom->tick, eeprom->scl,
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scl, eeprom->sda, sda);
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}
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eeprom->scl = scl;
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eeprom->sda = sda;
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}
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static uint64_t malta_fpga_read(void *opaque, hwaddr addr,
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unsigned size)
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{
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MaltaFPGAState *s = opaque;
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uint32_t val = 0;
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uint32_t saddr;
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saddr = (addr & 0xfffff);
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switch (saddr) {
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/* SWITCH Register */
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case 0x00200:
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val = 0x00000000;
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break;
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/* STATUS Register */
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case 0x00208:
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#if TARGET_BIG_ENDIAN
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val = 0x00000012;
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#else
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val = 0x00000010;
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#endif
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break;
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/* JMPRS Register */
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case 0x00210:
|
|
val = 0x00;
|
|
break;
|
|
|
|
/* LEDBAR Register */
|
|
case 0x00408:
|
|
val = s->leds;
|
|
break;
|
|
|
|
/* BRKRES Register */
|
|
case 0x00508:
|
|
val = s->brk;
|
|
break;
|
|
|
|
/* UART Registers are handled directly by the serial device */
|
|
|
|
/* GPOUT Register */
|
|
case 0x00a00:
|
|
val = s->gpout;
|
|
break;
|
|
|
|
/* XXX: implement a real I2C controller */
|
|
|
|
/* GPINP Register */
|
|
case 0x00a08:
|
|
/* IN = OUT until a real I2C control is implemented */
|
|
if (s->i2csel) {
|
|
val = s->i2cout;
|
|
} else {
|
|
val = 0x00;
|
|
}
|
|
break;
|
|
|
|
/* I2CINP Register */
|
|
case 0x00b00:
|
|
val = ((s->i2cin & ~1) | eeprom24c0x_read(&spd_eeprom));
|
|
break;
|
|
|
|
/* I2COE Register */
|
|
case 0x00b08:
|
|
val = s->i2coe;
|
|
break;
|
|
|
|
/* I2COUT Register */
|
|
case 0x00b10:
|
|
val = s->i2cout;
|
|
break;
|
|
|
|
/* I2CSEL Register */
|
|
case 0x00b18:
|
|
val = s->i2csel;
|
|
break;
|
|
|
|
default:
|
|
qemu_log_mask(LOG_GUEST_ERROR,
|
|
"malta_fpga_read: Bad register addr 0x%"HWADDR_PRIX"\n",
|
|
addr);
|
|
break;
|
|
}
|
|
return val;
|
|
}
|
|
|
|
static void malta_fpga_write(void *opaque, hwaddr addr,
|
|
uint64_t val, unsigned size)
|
|
{
|
|
MaltaFPGAState *s = opaque;
|
|
uint32_t saddr;
|
|
|
|
saddr = (addr & 0xfffff);
|
|
|
|
switch (saddr) {
|
|
|
|
/* SWITCH Register */
|
|
case 0x00200:
|
|
break;
|
|
|
|
/* JMPRS Register */
|
|
case 0x00210:
|
|
break;
|
|
|
|
/* LEDBAR Register */
|
|
case 0x00408:
|
|
s->leds = val & 0xff;
|
|
malta_fpga_update_display_leds(s);
|
|
break;
|
|
|
|
/* ASCIIWORD Register */
|
|
case 0x00410:
|
|
snprintf(s->display_text, 9, "%08X", (uint32_t)val);
|
|
malta_fpga_update_display_ascii(s);
|
|
break;
|
|
|
|
/* ASCIIPOS0 to ASCIIPOS7 Registers */
|
|
case 0x00418:
|
|
case 0x00420:
|
|
case 0x00428:
|
|
case 0x00430:
|
|
case 0x00438:
|
|
case 0x00440:
|
|
case 0x00448:
|
|
case 0x00450:
|
|
s->display_text[(saddr - 0x00418) >> 3] = (char) val;
|
|
malta_fpga_update_display_ascii(s);
|
|
break;
|
|
|
|
/* SOFTRES Register */
|
|
case 0x00500:
|
|
if (val == 0x42) {
|
|
qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
|
|
}
|
|
break;
|
|
|
|
/* BRKRES Register */
|
|
case 0x00508:
|
|
s->brk = val & 0xff;
|
|
break;
|
|
|
|
/* UART Registers are handled directly by the serial device */
|
|
|
|
/* GPOUT Register */
|
|
case 0x00a00:
|
|
s->gpout = val & 0xff;
|
|
break;
|
|
|
|
/* I2COE Register */
|
|
case 0x00b08:
|
|
s->i2coe = val & 0x03;
|
|
break;
|
|
|
|
/* I2COUT Register */
|
|
case 0x00b10:
|
|
eeprom24c0x_write(&spd_eeprom, val & 0x02, val & 0x01);
|
|
s->i2cout = val;
|
|
break;
|
|
|
|
/* I2CSEL Register */
|
|
case 0x00b18:
|
|
s->i2csel = val & 0x01;
|
|
break;
|
|
|
|
default:
|
|
qemu_log_mask(LOG_GUEST_ERROR,
|
|
"malta_fpga_write: Bad register addr 0x%"HWADDR_PRIX"\n",
|
|
addr);
|
|
break;
|
|
}
|
|
}
|
|
|
|
static const MemoryRegionOps malta_fpga_ops = {
|
|
.read = malta_fpga_read,
|
|
.write = malta_fpga_write,
|
|
.endianness = DEVICE_NATIVE_ENDIAN,
|
|
};
|
|
|
|
static void malta_fpga_reset(void *opaque)
|
|
{
|
|
MaltaFPGAState *s = opaque;
|
|
|
|
s->leds = 0x00;
|
|
s->brk = 0x0a;
|
|
s->gpout = 0x00;
|
|
s->i2cin = 0x3;
|
|
s->i2coe = 0x0;
|
|
s->i2cout = 0x3;
|
|
s->i2csel = 0x1;
|
|
|
|
s->display_text[8] = '\0';
|
|
snprintf(s->display_text, 9, " ");
|
|
}
|
|
|
|
static void malta_fgpa_display_event(void *opaque, QEMUChrEvent event)
|
|
{
|
|
MaltaFPGAState *s = opaque;
|
|
|
|
if (event == CHR_EVENT_OPENED && !s->display_inited) {
|
|
qemu_chr_fe_printf(&s->display, "\e[HMalta LEDBAR\r\n");
|
|
qemu_chr_fe_printf(&s->display, "+--------+\r\n");
|
|
qemu_chr_fe_printf(&s->display, "+ +\r\n");
|
|
qemu_chr_fe_printf(&s->display, "+--------+\r\n");
|
|
qemu_chr_fe_printf(&s->display, "\n");
|
|
qemu_chr_fe_printf(&s->display, "Malta ASCII\r\n");
|
|
qemu_chr_fe_printf(&s->display, "+--------+\r\n");
|
|
qemu_chr_fe_printf(&s->display, "+ +\r\n");
|
|
qemu_chr_fe_printf(&s->display, "+--------+\r\n");
|
|
s->display_inited = true;
|
|
}
|
|
}
|
|
|
|
static MaltaFPGAState *malta_fpga_init(MemoryRegion *address_space,
|
|
hwaddr base, qemu_irq uart_irq, Chardev *uart_chr)
|
|
{
|
|
MaltaFPGAState *s;
|
|
Chardev *chr;
|
|
|
|
s = g_new0(MaltaFPGAState, 1);
|
|
|
|
memory_region_init_io(&s->iomem, NULL, &malta_fpga_ops, s,
|
|
"malta-fpga", 0x100000);
|
|
memory_region_init_alias(&s->iomem_lo, NULL, "malta-fpga",
|
|
&s->iomem, 0, 0x900);
|
|
memory_region_init_alias(&s->iomem_hi, NULL, "malta-fpga",
|
|
&s->iomem, 0xa00, 0x100000 - 0xa00);
|
|
|
|
memory_region_add_subregion(address_space, base, &s->iomem_lo);
|
|
memory_region_add_subregion(address_space, base + 0xa00, &s->iomem_hi);
|
|
|
|
chr = qemu_chr_new("fpga", "vc:320x200", NULL);
|
|
qemu_chr_fe_init(&s->display, chr, NULL);
|
|
qemu_chr_fe_set_handlers(&s->display, NULL, NULL,
|
|
malta_fgpa_display_event, NULL, s, NULL, true);
|
|
|
|
s->uart = serial_mm_init(address_space, base + 0x900, 3, uart_irq,
|
|
230400, uart_chr, DEVICE_NATIVE_ENDIAN);
|
|
|
|
malta_fpga_reset(s);
|
|
qemu_register_reset(malta_fpga_reset, s);
|
|
|
|
return s;
|
|
}
|
|
|
|
/* Network support */
|
|
static void network_init(PCIBus *pci_bus)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < nb_nics; i++) {
|
|
NICInfo *nd = &nd_table[i];
|
|
const char *default_devaddr = NULL;
|
|
|
|
if (i == 0 && (!nd->model || strcmp(nd->model, "pcnet") == 0))
|
|
/* The malta board has a PCNet card using PCI SLOT 11 */
|
|
default_devaddr = "0b";
|
|
|
|
pci_nic_init_nofail(nd, pci_bus, "pcnet", default_devaddr);
|
|
}
|
|
}
|
|
|
|
static void bl_setup_gt64120_jump_kernel(void **p, uint64_t run_addr,
|
|
uint64_t kernel_entry)
|
|
{
|
|
static const char pci_pins_cfg[PCI_NUM_PINS] = {
|
|
10, 10, 11, 11 /* PIIX IRQRC[A:D] */
|
|
};
|
|
|
|
/* Bus endianness is always reversed */
|
|
#if TARGET_BIG_ENDIAN
|
|
#define cpu_to_gt32(x) (x)
|
|
#else
|
|
#define cpu_to_gt32(x) bswap32(x)
|
|
#endif
|
|
|
|
/* setup MEM-to-PCI0 mapping as done by YAMON */
|
|
|
|
/* move GT64120 registers from 0x14000000 to 0x1be00000 */
|
|
bl_gen_write_u32(p, /* GT_ISD */
|
|
cpu_mips_phys_to_kseg1(NULL, 0x14000000 + 0x68),
|
|
cpu_to_gt32(0x1be00000 << 3));
|
|
|
|
/* setup PCI0 io window to 0x18000000-0x181fffff */
|
|
bl_gen_write_u32(p, /* GT_PCI0IOLD */
|
|
cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x48),
|
|
cpu_to_gt32(0x18000000 << 3));
|
|
bl_gen_write_u32(p, /* GT_PCI0IOHD */
|
|
cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x50),
|
|
cpu_to_gt32(0x08000000 << 3));
|
|
|
|
/* setup PCI0 mem windows */
|
|
bl_gen_write_u32(p, /* GT_PCI0M0LD */
|
|
cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x58),
|
|
cpu_to_gt32(0x10000000 << 3));
|
|
bl_gen_write_u32(p, /* GT_PCI0M0HD */
|
|
cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x60),
|
|
cpu_to_gt32(0x07e00000 << 3));
|
|
bl_gen_write_u32(p, /* GT_PCI0M1LD */
|
|
cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x80),
|
|
cpu_to_gt32(0x18200000 << 3));
|
|
bl_gen_write_u32(p, /* GT_PCI0M1HD */
|
|
cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x88),
|
|
cpu_to_gt32(0x0bc00000 << 3));
|
|
|
|
#undef cpu_to_gt32
|
|
|
|
/*
|
|
* The PIIX ISA bridge is on PCI bus 0 dev 10 func 0.
|
|
* Load the PIIX IRQC[A:D] routing config address, then
|
|
* write routing configuration to the config data register.
|
|
*/
|
|
bl_gen_write_u32(p, /* GT_PCI0_CFGADDR */
|
|
cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0xcf8),
|
|
tswap32((1 << 31) /* ConfigEn */
|
|
| PCI_BUILD_BDF(0, PIIX4_PCI_DEVFN) << 8
|
|
| PIIX_PIRQCA));
|
|
bl_gen_write_u32(p, /* GT_PCI0_CFGDATA */
|
|
cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0xcfc),
|
|
tswap32(ldl_be_p(pci_pins_cfg)));
|
|
|
|
bl_gen_jump_kernel(p,
|
|
true, ENVP_VADDR - 64,
|
|
/*
|
|
* If semihosting is used, arguments have already
|
|
* been passed, so we preserve $a0.
|
|
*/
|
|
!semihosting_get_argc(), 2,
|
|
true, ENVP_VADDR,
|
|
true, ENVP_VADDR + 8,
|
|
true, loaderparams.ram_low_size,
|
|
kernel_entry);
|
|
}
|
|
|
|
static void write_bootloader_nanomips(uint8_t *base, uint64_t run_addr,
|
|
uint64_t kernel_entry)
|
|
{
|
|
uint16_t *p;
|
|
|
|
/* Small bootloader */
|
|
p = (uint16_t *)base;
|
|
|
|
stw_p(p++, 0x2800); stw_p(p++, 0x001c);
|
|
/* bc to_here */
|
|
stw_p(p++, 0x8000); stw_p(p++, 0xc000);
|
|
/* nop */
|
|
stw_p(p++, 0x8000); stw_p(p++, 0xc000);
|
|
/* nop */
|
|
stw_p(p++, 0x8000); stw_p(p++, 0xc000);
|
|
/* nop */
|
|
stw_p(p++, 0x8000); stw_p(p++, 0xc000);
|
|
/* nop */
|
|
stw_p(p++, 0x8000); stw_p(p++, 0xc000);
|
|
/* nop */
|
|
stw_p(p++, 0x8000); stw_p(p++, 0xc000);
|
|
/* nop */
|
|
stw_p(p++, 0x8000); stw_p(p++, 0xc000);
|
|
/* nop */
|
|
|
|
/* to_here: */
|
|
|
|
bl_setup_gt64120_jump_kernel((void **)&p, run_addr, kernel_entry);
|
|
}
|
|
|
|
/*
|
|
* ROM and pseudo bootloader
|
|
*
|
|
* The following code implements a very very simple bootloader. It first
|
|
* loads the registers a0 to a3 to the values expected by the OS, and
|
|
* then jump at the kernel address.
|
|
*
|
|
* The bootloader should pass the locations of the kernel arguments and
|
|
* environment variables tables. Those tables contain the 32-bit address
|
|
* of NULL terminated strings. The environment variables table should be
|
|
* terminated by a NULL address.
|
|
*
|
|
* For a simpler implementation, the number of kernel arguments is fixed
|
|
* to two (the name of the kernel and the command line), and the two
|
|
* tables are actually the same one.
|
|
*
|
|
* The registers a0 to a3 should contain the following values:
|
|
* a0 - number of kernel arguments
|
|
* a1 - 32-bit address of the kernel arguments table
|
|
* a2 - 32-bit address of the environment variables table
|
|
* a3 - RAM size in bytes
|
|
*/
|
|
static void write_bootloader(uint8_t *base, uint64_t run_addr,
|
|
uint64_t kernel_entry)
|
|
{
|
|
uint32_t *p;
|
|
|
|
/* Small bootloader */
|
|
p = (uint32_t *)base;
|
|
|
|
stl_p(p++, 0x08000000 | /* j 0x1fc00580 */
|
|
((run_addr + 0x580) & 0x0fffffff) >> 2);
|
|
stl_p(p++, 0x00000000); /* nop */
|
|
|
|
/* YAMON service vector */
|
|
stl_p(base + 0x500, run_addr + 0x0580); /* start: */
|
|
stl_p(base + 0x504, run_addr + 0x083c); /* print_count: */
|
|
stl_p(base + 0x520, run_addr + 0x0580); /* start: */
|
|
stl_p(base + 0x52c, run_addr + 0x0800); /* flush_cache: */
|
|
stl_p(base + 0x534, run_addr + 0x0808); /* print: */
|
|
stl_p(base + 0x538, run_addr + 0x0800); /* reg_cpu_isr: */
|
|
stl_p(base + 0x53c, run_addr + 0x0800); /* unred_cpu_isr: */
|
|
stl_p(base + 0x540, run_addr + 0x0800); /* reg_ic_isr: */
|
|
stl_p(base + 0x544, run_addr + 0x0800); /* unred_ic_isr: */
|
|
stl_p(base + 0x548, run_addr + 0x0800); /* reg_esr: */
|
|
stl_p(base + 0x54c, run_addr + 0x0800); /* unreg_esr: */
|
|
stl_p(base + 0x550, run_addr + 0x0800); /* getchar: */
|
|
stl_p(base + 0x554, run_addr + 0x0800); /* syscon_read: */
|
|
|
|
|
|
/* Second part of the bootloader */
|
|
p = (uint32_t *) (base + 0x580);
|
|
|
|
/*
|
|
* Load BAR registers as done by YAMON:
|
|
*
|
|
* - set up PCI0 I/O BARs from 0x18000000 to 0x181fffff
|
|
* - set up PCI0 MEM0 at 0x10000000, size 0x7e00000
|
|
* - set up PCI0 MEM1 at 0x18200000, size 0xbc00000
|
|
*
|
|
*/
|
|
|
|
bl_setup_gt64120_jump_kernel((void **)&p, run_addr, kernel_entry);
|
|
|
|
/* YAMON subroutines */
|
|
p = (uint32_t *) (base + 0x800);
|
|
stl_p(p++, 0x03e00009); /* jalr ra */
|
|
stl_p(p++, 0x24020000); /* li v0,0 */
|
|
/* 808 YAMON print */
|
|
stl_p(p++, 0x03e06821); /* move t5,ra */
|
|
stl_p(p++, 0x00805821); /* move t3,a0 */
|
|
stl_p(p++, 0x00a05021); /* move t2,a1 */
|
|
stl_p(p++, 0x91440000); /* lbu a0,0(t2) */
|
|
stl_p(p++, 0x254a0001); /* addiu t2,t2,1 */
|
|
stl_p(p++, 0x10800005); /* beqz a0,834 */
|
|
stl_p(p++, 0x00000000); /* nop */
|
|
stl_p(p++, 0x0ff0021c); /* jal 870 */
|
|
stl_p(p++, 0x00000000); /* nop */
|
|
stl_p(p++, 0x1000fff9); /* b 814 */
|
|
stl_p(p++, 0x00000000); /* nop */
|
|
stl_p(p++, 0x01a00009); /* jalr t5 */
|
|
stl_p(p++, 0x01602021); /* move a0,t3 */
|
|
/* 0x83c YAMON print_count */
|
|
stl_p(p++, 0x03e06821); /* move t5,ra */
|
|
stl_p(p++, 0x00805821); /* move t3,a0 */
|
|
stl_p(p++, 0x00a05021); /* move t2,a1 */
|
|
stl_p(p++, 0x00c06021); /* move t4,a2 */
|
|
stl_p(p++, 0x91440000); /* lbu a0,0(t2) */
|
|
stl_p(p++, 0x0ff0021c); /* jal 870 */
|
|
stl_p(p++, 0x00000000); /* nop */
|
|
stl_p(p++, 0x254a0001); /* addiu t2,t2,1 */
|
|
stl_p(p++, 0x258cffff); /* addiu t4,t4,-1 */
|
|
stl_p(p++, 0x1580fffa); /* bnez t4,84c */
|
|
stl_p(p++, 0x00000000); /* nop */
|
|
stl_p(p++, 0x01a00009); /* jalr t5 */
|
|
stl_p(p++, 0x01602021); /* move a0,t3 */
|
|
/* 0x870 */
|
|
stl_p(p++, 0x3c08b800); /* lui t0,0xb400 */
|
|
stl_p(p++, 0x350803f8); /* ori t0,t0,0x3f8 */
|
|
stl_p(p++, 0x91090005); /* lbu t1,5(t0) */
|
|
stl_p(p++, 0x00000000); /* nop */
|
|
stl_p(p++, 0x31290040); /* andi t1,t1,0x40 */
|
|
stl_p(p++, 0x1120fffc); /* beqz t1,878 <outch+0x8> */
|
|
stl_p(p++, 0x00000000); /* nop */
|
|
stl_p(p++, 0x03e00009); /* jalr ra */
|
|
stl_p(p++, 0xa1040000); /* sb a0,0(t0) */
|
|
}
|
|
|
|
static void G_GNUC_PRINTF(3, 4) prom_set(uint32_t *prom_buf, int index,
|
|
const char *string, ...)
|
|
{
|
|
va_list ap;
|
|
uint32_t table_addr;
|
|
|
|
if (index >= ENVP_NB_ENTRIES) {
|
|
return;
|
|
}
|
|
|
|
if (string == NULL) {
|
|
prom_buf[index] = 0;
|
|
return;
|
|
}
|
|
|
|
table_addr = sizeof(uint32_t) * ENVP_NB_ENTRIES + index * ENVP_ENTRY_SIZE;
|
|
prom_buf[index] = tswap32(ENVP_VADDR + table_addr);
|
|
|
|
va_start(ap, string);
|
|
vsnprintf((char *)prom_buf + table_addr, ENVP_ENTRY_SIZE, string, ap);
|
|
va_end(ap);
|
|
}
|
|
|
|
static void reinitialize_rng_seed(void *opaque)
|
|
{
|
|
char *rng_seed_hex = opaque;
|
|
uint8_t rng_seed[32];
|
|
|
|
qemu_guest_getrandom_nofail(rng_seed, sizeof(rng_seed));
|
|
for (size_t i = 0; i < sizeof(rng_seed); ++i) {
|
|
sprintf(rng_seed_hex + i * 2, "%02x", rng_seed[i]);
|
|
}
|
|
}
|
|
|
|
/* Kernel */
|
|
static uint64_t load_kernel(void)
|
|
{
|
|
uint64_t kernel_entry, kernel_high, initrd_size;
|
|
long kernel_size;
|
|
ram_addr_t initrd_offset;
|
|
uint32_t *prom_buf;
|
|
long prom_size;
|
|
int prom_index = 0;
|
|
uint8_t rng_seed[32];
|
|
char rng_seed_hex[sizeof(rng_seed) * 2 + 1];
|
|
size_t rng_seed_prom_offset;
|
|
|
|
kernel_size = load_elf(loaderparams.kernel_filename, NULL,
|
|
cpu_mips_kseg0_to_phys, NULL,
|
|
&kernel_entry, NULL,
|
|
&kernel_high, NULL, TARGET_BIG_ENDIAN, EM_MIPS,
|
|
1, 0);
|
|
if (kernel_size < 0) {
|
|
error_report("could not load kernel '%s': %s",
|
|
loaderparams.kernel_filename,
|
|
load_elf_strerror(kernel_size));
|
|
exit(1);
|
|
}
|
|
|
|
/* Check where the kernel has been linked */
|
|
if (kernel_entry <= USEG_LIMIT) {
|
|
error_report("Trap-and-Emul kernels (Linux CONFIG_KVM_GUEST)"
|
|
" are not supported");
|
|
exit(1);
|
|
}
|
|
|
|
/* load initrd */
|
|
initrd_size = 0;
|
|
initrd_offset = 0;
|
|
if (loaderparams.initrd_filename) {
|
|
initrd_size = get_image_size(loaderparams.initrd_filename);
|
|
if (initrd_size > 0) {
|
|
/*
|
|
* The kernel allocates the bootmap memory in the low memory after
|
|
* the initrd. It takes at most 128kiB for 2GB RAM and 4kiB
|
|
* pages.
|
|
*/
|
|
initrd_offset = ROUND_UP(loaderparams.ram_low_size
|
|
- (initrd_size + 128 * KiB),
|
|
INITRD_PAGE_SIZE);
|
|
if (kernel_high >= initrd_offset) {
|
|
error_report("memory too small for initial ram disk '%s'",
|
|
loaderparams.initrd_filename);
|
|
exit(1);
|
|
}
|
|
initrd_size = load_image_targphys(loaderparams.initrd_filename,
|
|
initrd_offset,
|
|
loaderparams.ram_size - initrd_offset);
|
|
}
|
|
if (initrd_size == (target_ulong) -1) {
|
|
error_report("could not load initial ram disk '%s'",
|
|
loaderparams.initrd_filename);
|
|
exit(1);
|
|
}
|
|
}
|
|
|
|
/* Setup prom parameters. */
|
|
prom_size = ENVP_NB_ENTRIES * (sizeof(int32_t) + ENVP_ENTRY_SIZE);
|
|
prom_buf = g_malloc(prom_size);
|
|
|
|
prom_set(prom_buf, prom_index++, "%s", loaderparams.kernel_filename);
|
|
if (initrd_size > 0) {
|
|
prom_set(prom_buf, prom_index++,
|
|
"rd_start=0x%" PRIx64 " rd_size=%" PRId64 " %s",
|
|
cpu_mips_phys_to_kseg0(NULL, initrd_offset),
|
|
initrd_size, loaderparams.kernel_cmdline);
|
|
} else {
|
|
prom_set(prom_buf, prom_index++, "%s", loaderparams.kernel_cmdline);
|
|
}
|
|
|
|
prom_set(prom_buf, prom_index++, "memsize");
|
|
prom_set(prom_buf, prom_index++, "%u", loaderparams.ram_low_size);
|
|
|
|
prom_set(prom_buf, prom_index++, "ememsize");
|
|
prom_set(prom_buf, prom_index++, "%u", loaderparams.ram_size);
|
|
|
|
prom_set(prom_buf, prom_index++, "modetty0");
|
|
prom_set(prom_buf, prom_index++, "38400n8r");
|
|
|
|
qemu_guest_getrandom_nofail(rng_seed, sizeof(rng_seed));
|
|
for (size_t i = 0; i < sizeof(rng_seed); ++i) {
|
|
sprintf(rng_seed_hex + i * 2, "%02x", rng_seed[i]);
|
|
}
|
|
prom_set(prom_buf, prom_index++, "rngseed");
|
|
rng_seed_prom_offset = prom_index * ENVP_ENTRY_SIZE +
|
|
sizeof(uint32_t) * ENVP_NB_ENTRIES;
|
|
prom_set(prom_buf, prom_index++, "%s", rng_seed_hex);
|
|
|
|
prom_set(prom_buf, prom_index++, NULL);
|
|
|
|
rom_add_blob_fixed("prom", prom_buf, prom_size, ENVP_PADDR);
|
|
qemu_register_reset_nosnapshotload(reinitialize_rng_seed,
|
|
rom_ptr(ENVP_PADDR, prom_size) + rng_seed_prom_offset);
|
|
|
|
g_free(prom_buf);
|
|
return kernel_entry;
|
|
}
|
|
|
|
static void malta_mips_config(MIPSCPU *cpu)
|
|
{
|
|
MachineState *ms = MACHINE(qdev_get_machine());
|
|
unsigned int smp_cpus = ms->smp.cpus;
|
|
CPUMIPSState *env = &cpu->env;
|
|
CPUState *cs = CPU(cpu);
|
|
|
|
if (ase_mt_available(env)) {
|
|
env->mvp->CP0_MVPConf0 = deposit32(env->mvp->CP0_MVPConf0,
|
|
CP0MVPC0_PTC, 8,
|
|
smp_cpus * cs->nr_threads - 1);
|
|
env->mvp->CP0_MVPConf0 = deposit32(env->mvp->CP0_MVPConf0,
|
|
CP0MVPC0_PVPE, 4, smp_cpus - 1);
|
|
}
|
|
}
|
|
|
|
static int malta_pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num)
|
|
{
|
|
int slot;
|
|
|
|
slot = PCI_SLOT(pci_dev->devfn);
|
|
|
|
switch (slot) {
|
|
/* PIIX4 USB */
|
|
case 10:
|
|
return 3;
|
|
/* AMD 79C973 Ethernet */
|
|
case 11:
|
|
return 1;
|
|
/* Crystal 4281 Sound */
|
|
case 12:
|
|
return 2;
|
|
/* PCI slot 1 to 4 */
|
|
case 18 ... 21:
|
|
return ((slot - 18) + irq_num) & 0x03;
|
|
/* Unknown device, don't do any translation */
|
|
default:
|
|
return irq_num;
|
|
}
|
|
}
|
|
|
|
static void main_cpu_reset(void *opaque)
|
|
{
|
|
MIPSCPU *cpu = opaque;
|
|
CPUMIPSState *env = &cpu->env;
|
|
|
|
cpu_reset(CPU(cpu));
|
|
|
|
/*
|
|
* The bootloader does not need to be rewritten as it is located in a
|
|
* read only location. The kernel location and the arguments table
|
|
* location does not change.
|
|
*/
|
|
if (loaderparams.kernel_filename) {
|
|
env->CP0_Status &= ~(1 << CP0St_ERL);
|
|
}
|
|
|
|
malta_mips_config(cpu);
|
|
}
|
|
|
|
static void create_cpu_without_cps(MachineState *ms, MaltaState *s,
|
|
qemu_irq *cbus_irq, qemu_irq *i8259_irq)
|
|
{
|
|
CPUMIPSState *env;
|
|
MIPSCPU *cpu;
|
|
int i;
|
|
|
|
for (i = 0; i < ms->smp.cpus; i++) {
|
|
cpu = mips_cpu_create_with_clock(ms->cpu_type, s->cpuclk);
|
|
|
|
/* Init internal devices */
|
|
cpu_mips_irq_init_cpu(cpu);
|
|
cpu_mips_clock_init(cpu);
|
|
qemu_register_reset(main_cpu_reset, cpu);
|
|
}
|
|
|
|
cpu = MIPS_CPU(first_cpu);
|
|
env = &cpu->env;
|
|
*i8259_irq = env->irq[2];
|
|
*cbus_irq = env->irq[4];
|
|
}
|
|
|
|
static void create_cps(MachineState *ms, MaltaState *s,
|
|
qemu_irq *cbus_irq, qemu_irq *i8259_irq)
|
|
{
|
|
object_initialize_child(OBJECT(s), "cps", &s->cps, TYPE_MIPS_CPS);
|
|
object_property_set_str(OBJECT(&s->cps), "cpu-type", ms->cpu_type,
|
|
&error_fatal);
|
|
object_property_set_uint(OBJECT(&s->cps), "num-vp", ms->smp.cpus,
|
|
&error_fatal);
|
|
qdev_connect_clock_in(DEVICE(&s->cps), "clk-in", s->cpuclk);
|
|
sysbus_realize(SYS_BUS_DEVICE(&s->cps), &error_fatal);
|
|
|
|
sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->cps), 0, 0, 1);
|
|
|
|
*i8259_irq = get_cps_irq(&s->cps, 3);
|
|
*cbus_irq = NULL;
|
|
}
|
|
|
|
static void mips_create_cpu(MachineState *ms, MaltaState *s,
|
|
qemu_irq *cbus_irq, qemu_irq *i8259_irq)
|
|
{
|
|
if ((ms->smp.cpus > 1) && cpu_type_supports_cps_smp(ms->cpu_type)) {
|
|
create_cps(ms, s, cbus_irq, i8259_irq);
|
|
} else {
|
|
create_cpu_without_cps(ms, s, cbus_irq, i8259_irq);
|
|
}
|
|
}
|
|
|
|
static
|
|
void mips_malta_init(MachineState *machine)
|
|
{
|
|
ram_addr_t ram_size = machine->ram_size;
|
|
ram_addr_t ram_low_size;
|
|
const char *kernel_filename = machine->kernel_filename;
|
|
const char *kernel_cmdline = machine->kernel_cmdline;
|
|
const char *initrd_filename = machine->initrd_filename;
|
|
char *filename;
|
|
PFlashCFI01 *fl;
|
|
MemoryRegion *system_memory = get_system_memory();
|
|
MemoryRegion *ram_low_preio = g_new(MemoryRegion, 1);
|
|
MemoryRegion *ram_low_postio;
|
|
MemoryRegion *bios, *bios_copy = g_new(MemoryRegion, 1);
|
|
const size_t smbus_eeprom_size = 8 * 256;
|
|
uint8_t *smbus_eeprom_buf = g_malloc0(smbus_eeprom_size);
|
|
uint64_t kernel_entry, bootloader_run_addr;
|
|
PCIBus *pci_bus;
|
|
ISABus *isa_bus;
|
|
qemu_irq cbus_irq, i8259_irq;
|
|
I2CBus *smbus;
|
|
DriveInfo *dinfo;
|
|
int fl_idx = 0;
|
|
MaltaState *s;
|
|
PCIDevice *piix4;
|
|
DeviceState *dev;
|
|
|
|
s = MIPS_MALTA(qdev_new(TYPE_MIPS_MALTA));
|
|
sysbus_realize_and_unref(SYS_BUS_DEVICE(s), &error_fatal);
|
|
|
|
/* create CPU */
|
|
mips_create_cpu(machine, s, &cbus_irq, &i8259_irq);
|
|
|
|
/* allocate RAM */
|
|
if (ram_size > 2 * GiB) {
|
|
error_report("Too much memory for this machine: %" PRId64 "MB,"
|
|
" maximum 2048MB", ram_size / MiB);
|
|
exit(1);
|
|
}
|
|
|
|
/* register RAM at high address where it is undisturbed by IO */
|
|
memory_region_add_subregion(system_memory, 0x80000000, machine->ram);
|
|
|
|
/* alias for pre IO hole access */
|
|
memory_region_init_alias(ram_low_preio, NULL, "mips_malta_low_preio.ram",
|
|
machine->ram, 0, MIN(ram_size, 256 * MiB));
|
|
memory_region_add_subregion(system_memory, 0, ram_low_preio);
|
|
|
|
/* alias for post IO hole access, if there is enough RAM */
|
|
if (ram_size > 512 * MiB) {
|
|
ram_low_postio = g_new(MemoryRegion, 1);
|
|
memory_region_init_alias(ram_low_postio, NULL,
|
|
"mips_malta_low_postio.ram",
|
|
machine->ram, 512 * MiB,
|
|
ram_size - 512 * MiB);
|
|
memory_region_add_subregion(system_memory, 512 * MiB,
|
|
ram_low_postio);
|
|
}
|
|
|
|
/* FPGA */
|
|
|
|
/* The CBUS UART is attached to the MIPS CPU INT2 pin, ie interrupt 4 */
|
|
malta_fpga_init(system_memory, FPGA_ADDRESS, cbus_irq, serial_hd(2));
|
|
|
|
/* Load firmware in flash / BIOS. */
|
|
dinfo = drive_get(IF_PFLASH, 0, fl_idx);
|
|
fl = pflash_cfi01_register(FLASH_ADDRESS, "mips_malta.bios",
|
|
FLASH_SIZE,
|
|
dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
|
|
65536,
|
|
4, 0x0000, 0x0000, 0x0000, 0x0000,
|
|
TARGET_BIG_ENDIAN);
|
|
bios = pflash_cfi01_get_memory(fl);
|
|
fl_idx++;
|
|
if (kernel_filename) {
|
|
ram_low_size = MIN(ram_size, 256 * MiB);
|
|
bootloader_run_addr = cpu_mips_phys_to_kseg0(NULL, RESET_ADDRESS);
|
|
|
|
/* Write a small bootloader to the flash location. */
|
|
loaderparams.ram_size = ram_size;
|
|
loaderparams.ram_low_size = ram_low_size;
|
|
loaderparams.kernel_filename = kernel_filename;
|
|
loaderparams.kernel_cmdline = kernel_cmdline;
|
|
loaderparams.initrd_filename = initrd_filename;
|
|
kernel_entry = load_kernel();
|
|
|
|
if (!cpu_type_supports_isa(machine->cpu_type, ISA_NANOMIPS32)) {
|
|
write_bootloader(memory_region_get_ram_ptr(bios),
|
|
bootloader_run_addr, kernel_entry);
|
|
} else {
|
|
write_bootloader_nanomips(memory_region_get_ram_ptr(bios),
|
|
bootloader_run_addr, kernel_entry);
|
|
}
|
|
} else {
|
|
target_long bios_size = FLASH_SIZE;
|
|
/* Load firmware from flash. */
|
|
if (!dinfo) {
|
|
/* Load a BIOS image. */
|
|
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS,
|
|
machine->firmware ?: BIOS_FILENAME);
|
|
if (filename) {
|
|
bios_size = load_image_targphys(filename, FLASH_ADDRESS,
|
|
BIOS_SIZE);
|
|
g_free(filename);
|
|
} else {
|
|
bios_size = -1;
|
|
}
|
|
if ((bios_size < 0 || bios_size > BIOS_SIZE) &&
|
|
machine->firmware && !qtest_enabled()) {
|
|
error_report("Could not load MIPS bios '%s'", machine->firmware);
|
|
exit(1);
|
|
}
|
|
}
|
|
/*
|
|
* In little endian mode the 32bit words in the bios are swapped,
|
|
* a neat trick which allows bi-endian firmware.
|
|
*/
|
|
#if !TARGET_BIG_ENDIAN
|
|
{
|
|
uint32_t *end, *addr;
|
|
const size_t swapsize = MIN(bios_size, 0x3e0000);
|
|
addr = rom_ptr(FLASH_ADDRESS, swapsize);
|
|
if (!addr) {
|
|
addr = memory_region_get_ram_ptr(bios);
|
|
}
|
|
end = (void *)addr + swapsize;
|
|
while (addr < end) {
|
|
bswap32s(addr);
|
|
addr++;
|
|
}
|
|
}
|
|
#endif
|
|
}
|
|
|
|
/*
|
|
* Map the BIOS at a 2nd physical location, as on the real board.
|
|
* Copy it so that we can patch in the MIPS revision, which cannot be
|
|
* handled by an overlapping region as the resulting ROM code subpage
|
|
* regions are not executable.
|
|
*/
|
|
memory_region_init_ram(bios_copy, NULL, "bios.1fc", BIOS_SIZE,
|
|
&error_fatal);
|
|
if (!rom_copy(memory_region_get_ram_ptr(bios_copy),
|
|
FLASH_ADDRESS, BIOS_SIZE)) {
|
|
memcpy(memory_region_get_ram_ptr(bios_copy),
|
|
memory_region_get_ram_ptr(bios), BIOS_SIZE);
|
|
}
|
|
memory_region_set_readonly(bios_copy, true);
|
|
memory_region_add_subregion(system_memory, RESET_ADDRESS, bios_copy);
|
|
|
|
/* Board ID = 0x420 (Malta Board with CoreLV) */
|
|
stl_p(memory_region_get_ram_ptr(bios_copy) + 0x10, 0x00000420);
|
|
|
|
/* Northbridge */
|
|
dev = qdev_new("gt64120");
|
|
qdev_prop_set_bit(dev, "cpu-little-endian", !TARGET_BIG_ENDIAN);
|
|
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
|
|
pci_bus = PCI_BUS(qdev_get_child_bus(dev, "pci"));
|
|
pci_bus_map_irqs(pci_bus, malta_pci_slot_get_pirq);
|
|
|
|
/* Southbridge */
|
|
piix4 = pci_new_multifunction(PIIX4_PCI_DEVFN, TYPE_PIIX4_PCI_DEVICE);
|
|
qdev_prop_set_uint32(DEVICE(piix4), "smb_io_base", 0x1100);
|
|
pci_realize_and_unref(piix4, pci_bus, &error_fatal);
|
|
isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix4), "isa.0"));
|
|
|
|
dev = DEVICE(object_resolve_path_component(OBJECT(piix4), "ide"));
|
|
pci_ide_create_devs(PCI_DEVICE(dev));
|
|
|
|
/* Interrupt controller */
|
|
qdev_connect_gpio_out_named(DEVICE(piix4), "intr", 0, i8259_irq);
|
|
|
|
/* generate SPD EEPROM data */
|
|
dev = DEVICE(object_resolve_path_component(OBJECT(piix4), "pm"));
|
|
smbus = I2C_BUS(qdev_get_child_bus(dev, "i2c"));
|
|
generate_eeprom_spd(&smbus_eeprom_buf[0 * 256], ram_size);
|
|
generate_eeprom_serial(&smbus_eeprom_buf[6 * 256]);
|
|
smbus_eeprom_init(smbus, 8, smbus_eeprom_buf, smbus_eeprom_size);
|
|
g_free(smbus_eeprom_buf);
|
|
|
|
/* Super I/O: SMS FDC37M817 */
|
|
isa_create_simple(isa_bus, TYPE_FDC37M81X_SUPERIO);
|
|
|
|
/* Network card */
|
|
network_init(pci_bus);
|
|
|
|
/* Optional PCI video card */
|
|
pci_vga_init(pci_bus);
|
|
}
|
|
|
|
static void mips_malta_instance_init(Object *obj)
|
|
{
|
|
MaltaState *s = MIPS_MALTA(obj);
|
|
|
|
s->cpuclk = qdev_init_clock_out(DEVICE(obj), "cpu-refclk");
|
|
clock_set_hz(s->cpuclk, 320000000); /* 320 MHz */
|
|
}
|
|
|
|
static const TypeInfo mips_malta_device = {
|
|
.name = TYPE_MIPS_MALTA,
|
|
.parent = TYPE_SYS_BUS_DEVICE,
|
|
.instance_size = sizeof(MaltaState),
|
|
.instance_init = mips_malta_instance_init,
|
|
};
|
|
|
|
GlobalProperty malta_compat[] = {
|
|
{ "PIIX4_PM", "memory-hotplug-support", "off" },
|
|
{ "PIIX4_PM", "acpi-pci-hotplug-with-bridge-support", "off" },
|
|
{ "PIIX4_PM", "acpi-root-pci-hotplug", "off" },
|
|
{ "PIIX4_PM", "x-not-migrate-acpi-index", "true" },
|
|
};
|
|
const size_t malta_compat_len = G_N_ELEMENTS(malta_compat);
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static void mips_malta_machine_init(MachineClass *mc)
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{
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mc->desc = "MIPS Malta Core LV";
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mc->init = mips_malta_init;
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mc->block_default_type = IF_IDE;
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mc->max_cpus = 16;
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mc->is_default = true;
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#ifdef TARGET_MIPS64
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mc->default_cpu_type = MIPS_CPU_TYPE_NAME("20Kc");
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#else
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mc->default_cpu_type = MIPS_CPU_TYPE_NAME("24Kf");
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#endif
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mc->default_ram_id = "mips_malta.ram";
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compat_props_add(mc->compat_props, malta_compat, malta_compat_len);
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}
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DEFINE_MACHINE("malta", mips_malta_machine_init)
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static void mips_malta_register_types(void)
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{
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type_register_static(&mips_malta_device);
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}
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type_init(mips_malta_register_types)
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