Peter Maydell 65cc5ccf06 Second RISC-V PR for QEMU 8.0 ... * riscv_htif: Support console output via proxy syscall * Cleanup firmware and device tree loading * Fix elen check when using vector extensions * add RISC-V OpenSBI boot test * Ensure we always follow MISA parsing * Fix up masking of vsip/vsie accesses * Trap on writes to stimecmp from VS when hvictl.VTI=1 * Introduce helper_set_rounding_mode_chkfrm -----BEGIN PGP SIGNATURE----- iQEzBAABCAAdFiEE9sSsRtSTSGjTuM6PIeENKd+XcFQFAmPKRP0ACgkQIeENKd+X cFTHTwgAkyRDxrLepvI0KNaT0+cUBh+3QFlJ5JRtVnDW+5R+3aGT72PTS7Migqoh H3IFCB2mcSdQvyjj2jDFlrFd0oVIaqE0+bnhouS/4nHB5S/vmapHi4Mc74Vv1CMB rgXScL+C5gDOH1I7XjqOb1FY5Vxqyhi3IzdIoj+0ysUrGmUkqx+ij/cfQL7jkH9Q slNAkorgwgrTgMgkJ5RKd4cjyv35O4XKLAsgixVTfJ+WcxKmc/zaJOkNM/UDnmxK k2+2P8bshZWtWscXbm3oMC5+2ow1QtFedEkhHqb4adkQIyolKL7P1TfMlCgMSvES BKl0DUhqQ+7F77tik3GPy9spQ6LpTQ== =ifFF -----END PGP SIGNATURE----- Merge tag 'pull-riscv-to-apply-20230120' of https://github.com/alistair23/qemu into staging Second RISC-V PR for QEMU 8.0 * riscv_htif: Support console output via proxy syscall * Cleanup firmware and device tree loading * Fix elen check when using vector extensions * add RISC-V OpenSBI boot test * Ensure we always follow MISA parsing * Fix up masking of vsip/vsie accesses * Trap on writes to stimecmp from VS when hvictl.VTI=1 * Introduce helper_set_rounding_mode_chkfrm # -----BEGIN PGP SIGNATURE----- # # iQEzBAABCAAdFiEE9sSsRtSTSGjTuM6PIeENKd+XcFQFAmPKRP0ACgkQIeENKd+X # cFTHTwgAkyRDxrLepvI0KNaT0+cUBh+3QFlJ5JRtVnDW+5R+3aGT72PTS7Migqoh # H3IFCB2mcSdQvyjj2jDFlrFd0oVIaqE0+bnhouS/4nHB5S/vmapHi4Mc74Vv1CMB # rgXScL+C5gDOH1I7XjqOb1FY5Vxqyhi3IzdIoj+0ysUrGmUkqx+ij/cfQL7jkH9Q # slNAkorgwgrTgMgkJ5RKd4cjyv35O4XKLAsgixVTfJ+WcxKmc/zaJOkNM/UDnmxK # k2+2P8bshZWtWscXbm3oMC5+2ow1QtFedEkhHqb4adkQIyolKL7P1TfMlCgMSvES # BKl0DUhqQ+7F77tik3GPy9spQ6LpTQ== # =ifFF # -----END PGP SIGNATURE----- # gpg: Signature made Fri 20 Jan 2023 07:38:37 GMT # gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054 # gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full] # Primary key fingerprint: F6C4 AC46 D493 4868 D3B8 CE8F 21E1 0D29 DF97 7054 * tag 'pull-riscv-to-apply-20230120' of https://github.com/alistair23/qemu: (37 commits) hw/riscv/virt.c: move create_fw_cfg() back to virt_machine_init() target/riscv: Remove helper_set_rod_rounding_mode target/riscv: Introduce helper_set_rounding_mode_chkfrm tcg/riscv: Use tcg_pcrel_diff in tcg_out_ldst target/riscv: Trap on writes to stimecmp from VS when hvictl.VTI=1 target/riscv: Fix up masking of vsip/vsie accesses hw/riscv: use ms->fdt in riscv_socket_fdt_write_distance_matrix() hw/riscv: use MachineState::fdt in riscv_socket_fdt_write_id() hw/riscv/virt.c: remove 'is_32_bit' param from create_fdt_socket_cpus() hw/riscv/sifive_u.c: simplify create_fdt() hw/riscv/virt.c: simplify create_fdt() hw/riscv/spike.c: simplify create_fdt() target/riscv: Use TARGET_FMT_lx for env->mhartid target/riscv/cpu.c: do not skip misa logic in riscv_cpu_realize() target/riscv/cpu: set cpu->cfg in register_cpu_props() hw/riscv/boot.c: use MachineState in riscv_load_kernel() hw/riscv/boot.c: use MachineState in riscv_load_initrd() hw/riscv: write bootargs 'chosen' FDT after riscv_load_kernel() hw/riscv: write initrd 'chosen' FDT inside riscv_load_initrd() hw/riscv/spike.c: load initrd right after riscv_load_kernel() ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>		2023-01-20 16:17:56 +00:00
..
avocado
bench
data
decode
docker
fp
guest-debug
image-fuzzer
include
keys
lcitool
migration
multiboot
perf/block/qcow2
plugin
qapi-schema
qemu-iotests
qtest
rocker
tcg
tsan
uefi-test-tools
unit	Header cleanup patches for 2023-01-20	2023-01-20 13:17:55 +00:00
vm
vmstate-static-checker-data
check-block.sh
dbus-vmstate-daemon.sh
Makefile.include
meson.build
requirements.txt
test-qht-par.c
vhost-user-bridge.c