bc7a45ab88
ISA 3.0B added a set of Floating-Point Status and Control Register (FPSCR) instructions: mffsce, mffscdrn, mffscdrni, mffscrn, mffscrni, mffsl. This patch adds support for 'mffsce' instruction. 'mffsce' is identical to 'mffs', except that it also clears the exception enable bits in the FPSCR. On CPUs without support for 'mffsce' (below ISA 3.0), the instruction will execute identically to 'mffs'. Signed-off-by: Paul A. Clarke <pc@us.ibm.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <1568817082-1384-1-git-send-email-pc@us.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au> |
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| .. | ||
| dfp-impl.inc.c | ||
| dfp-ops.inc.c | ||
| fp-impl.inc.c | ||
| fp-ops.inc.c | ||
| spe-impl.inc.c | ||
| spe-ops.inc.c | ||
| vmx-impl.inc.c | ||
| vmx-ops.inc.c | ||
| vsx-impl.inc.c | ||
| vsx-ops.inc.c | ||