qemu-e2k/target
Peter Maydell 53ae2fdef1 target/arm: Don't set syndrome ISS for loads and stores with writeback
The architecture requires that for faults on loads and stores which
do writeback, the syndrome information does not have the ISS
instruction syndrome information (i.e. ISV is 0).  We got this wrong
for the load and store instructions covered by disas_ldst_reg_imm9().
Calculate iss_valid correctly so that if the insn is a writeback one
it is false.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1057
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220715123323.1550983-1-peter.maydell@linaro.org
2022-07-18 13:20:14 +01:00
..
alpha
arm target/arm: Don't set syndrome ISS for loads and stores with writeback 2022-07-18 13:20:14 +01:00
avr
cris
hexagon
hppa
i386 hvf: Enable RDTSCP support 2022-07-13 00:05:39 +02:00
loongarch
m68k
microblaze
mips target/mips: Remove GET_TARGET_STRING and FREE_TARGET_STRING 2022-07-12 22:32:22 +02:00
nios2
openrisc
ppc target/ppc: Fix MPC8555 and MPC8560 core type to e500v1 2022-07-06 10:30:01 -03:00
riscv
rx
s390x target/s390x: Exit tb after executing ex_value 2022-07-06 19:04:57 +02:00
sh4
sparc
tricore
xtensa
Kconfig
meson.build