7d8ccf58d5
To avoid overflow if larger values are added later use ram_addr_t for the sdram_bank_sizes parameter to match ram_size to which it is compared. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
476 lines
15 KiB
C
476 lines
15 KiB
C
/*
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* QEMU aCube Sam460ex board emulation
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*
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* Copyright (c) 2012 François Revol
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* Copyright (c) 2016-2019 BALATON Zoltan
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*
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* This file is derived from hw/ppc440_bamboo.c,
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* the copyright for that material belongs to the original owners.
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*
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* This work is licensed under the GNU GPL license version 2 or later.
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*
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*/
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#include "qemu/osdep.h"
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#include "qemu/units.h"
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#include "qemu-common.h"
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#include "qemu/error-report.h"
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#include "qapi/error.h"
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#include "hw/hw.h"
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#include "hw/boards.h"
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#include "sysemu/kvm.h"
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#include "kvm_ppc.h"
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#include "sysemu/device_tree.h"
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#include "sysemu/block-backend.h"
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#include "hw/loader.h"
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#include "elf.h"
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#include "exec/address-spaces.h"
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#include "exec/memory.h"
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#include "ppc440.h"
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#include "ppc405.h"
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#include "hw/block/flash.h"
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#include "sysemu/sysemu.h"
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#include "sysemu/qtest.h"
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#include "hw/sysbus.h"
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#include "hw/char/serial.h"
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#include "hw/i2c/ppc4xx_i2c.h"
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#include "hw/i2c/smbus.h"
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#include "hw/usb/hcd-ehci.h"
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#include "hw/ppc/fdt.h"
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#include <libfdt.h>
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#define BINARY_DEVICE_TREE_FILE "canyonlands.dtb"
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#define UBOOT_FILENAME "u-boot-sam460-20100605.bin"
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/* to extract the official U-Boot bin from the updater: */
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/* dd bs=1 skip=$(($(stat -c '%s' updater/updater-460) - 0x80000)) \
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if=updater/updater-460 of=u-boot-sam460-20100605.bin */
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/* from Sam460 U-Boot include/configs/Sam460ex.h */
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#define FLASH_BASE 0xfff00000
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#define FLASH_BASE_H 0x4
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#define FLASH_SIZE (1 * MiB)
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#define UBOOT_LOAD_BASE 0xfff80000
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#define UBOOT_SIZE 0x00080000
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#define UBOOT_ENTRY 0xfffffffc
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/* from U-Boot */
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#define EPAPR_MAGIC (0x45504150)
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#define KERNEL_ADDR 0x1000000
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#define FDT_ADDR 0x1800000
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#define RAMDISK_ADDR 0x1900000
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/* Sam460ex IRQ MAP:
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IRQ0 = ETH_INT
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IRQ1 = FPGA_INT
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IRQ2 = PCI_INT (PCIA, PCIB, PCIC, PCIB)
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IRQ3 = FPGA_INT2
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IRQ11 = RTC_INT
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IRQ12 = SM502_INT
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*/
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#define CPU_FREQ 1150000000
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#define PLB_FREQ 230000000
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#define OPB_FREQ 115000000
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#define EBC_FREQ 115000000
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#define UART_FREQ 11059200
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#define SDRAM_NR_BANKS 4
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/* FIXME: See u-boot.git 8ac41e, also fix in ppc440_uc.c */
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static const ram_addr_t ppc460ex_sdram_bank_sizes[] = {
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1 * GiB, 512 * MiB, 256 * MiB, 128 * MiB, 64 * MiB, 32 * MiB, 0
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};
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struct boot_info {
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uint32_t dt_base;
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uint32_t dt_size;
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uint32_t entry;
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};
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static int sam460ex_load_uboot(void)
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{
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DriveInfo *dinfo;
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BlockBackend *blk = NULL;
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hwaddr base = FLASH_BASE | ((hwaddr)FLASH_BASE_H << 32);
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long bios_size = FLASH_SIZE;
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int fl_sectors;
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dinfo = drive_get(IF_PFLASH, 0, 0);
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if (dinfo) {
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blk = blk_by_legacy_dinfo(dinfo);
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bios_size = blk_getlength(blk);
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}
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fl_sectors = (bios_size + 65535) >> 16;
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if (!pflash_cfi01_register(base, NULL, "sam460ex.flash", bios_size,
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blk, 64 * KiB, fl_sectors,
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1, 0x89, 0x18, 0x0000, 0x0, 1)) {
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error_report("Error registering flash memory");
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/* XXX: return an error instead? */
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exit(1);
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}
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if (!blk) {
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/*error_report("No flash image given with the 'pflash' parameter,"
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" using default u-boot image");*/
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base = UBOOT_LOAD_BASE | ((hwaddr)FLASH_BASE_H << 32);
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rom_add_file_fixed(UBOOT_FILENAME, base, -1);
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}
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return 0;
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}
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static int sam460ex_load_device_tree(hwaddr addr,
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uint32_t ramsize,
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hwaddr initrd_base,
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hwaddr initrd_size,
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const char *kernel_cmdline)
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{
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uint32_t mem_reg_property[] = { 0, 0, cpu_to_be32(ramsize) };
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char *filename;
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int fdt_size;
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void *fdt;
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uint32_t tb_freq = CPU_FREQ;
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uint32_t clock_freq = CPU_FREQ;
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int offset;
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filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, BINARY_DEVICE_TREE_FILE);
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if (!filename) {
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error_report("Couldn't find dtb file `%s'", BINARY_DEVICE_TREE_FILE);
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exit(1);
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}
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fdt = load_device_tree(filename, &fdt_size);
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if (!fdt) {
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error_report("Couldn't load dtb file `%s'", filename);
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g_free(filename);
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exit(1);
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}
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g_free(filename);
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/* Manipulate device tree in memory. */
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qemu_fdt_setprop(fdt, "/memory", "reg", mem_reg_property,
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sizeof(mem_reg_property));
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/* default FDT doesn't have a /chosen node... */
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qemu_fdt_add_subnode(fdt, "/chosen");
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qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", initrd_base);
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qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end",
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(initrd_base + initrd_size));
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qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", kernel_cmdline);
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/* Copy data from the host device tree into the guest. Since the guest can
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* directly access the timebase without host involvement, we must expose
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* the correct frequencies. */
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if (kvm_enabled()) {
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tb_freq = kvmppc_get_tbfreq();
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clock_freq = kvmppc_get_clockfreq();
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}
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qemu_fdt_setprop_cell(fdt, "/cpus/cpu@0", "clock-frequency",
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clock_freq);
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qemu_fdt_setprop_cell(fdt, "/cpus/cpu@0", "timebase-frequency",
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tb_freq);
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/* Remove cpm node if it exists (it is not emulated) */
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offset = fdt_path_offset(fdt, "/cpm");
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if (offset >= 0) {
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_FDT(fdt_nop_node(fdt, offset));
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}
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/* set serial port clocks */
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offset = fdt_node_offset_by_compatible(fdt, -1, "ns16550");
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while (offset >= 0) {
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_FDT(fdt_setprop_cell(fdt, offset, "clock-frequency", UART_FREQ));
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offset = fdt_node_offset_by_compatible(fdt, offset, "ns16550");
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}
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/* some more clocks */
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qemu_fdt_setprop_cell(fdt, "/plb", "clock-frequency",
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PLB_FREQ);
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qemu_fdt_setprop_cell(fdt, "/plb/opb", "clock-frequency",
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OPB_FREQ);
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qemu_fdt_setprop_cell(fdt, "/plb/opb/ebc", "clock-frequency",
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EBC_FREQ);
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rom_add_blob_fixed(BINARY_DEVICE_TREE_FILE, fdt, fdt_size, addr);
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g_free(fdt);
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return fdt_size;
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}
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/* Create reset TLB entries for BookE, mapping only the flash memory. */
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static void mmubooke_create_initial_mapping_uboot(CPUPPCState *env)
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{
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ppcemb_tlb_t *tlb = &env->tlb.tlbe[0];
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/* on reset the flash is mapped by a shadow TLB,
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* but since we don't implement them we need to use
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* the same values U-Boot will use to avoid a fault.
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*/
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tlb->attr = 0;
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tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4);
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tlb->size = 0x10000000; /* up to 0xffffffff */
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tlb->EPN = 0xf0000000 & TARGET_PAGE_MASK;
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tlb->RPN = (0xf0000000 & TARGET_PAGE_MASK) | 0x4;
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tlb->PID = 0;
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}
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/* Create reset TLB entries for BookE, spanning the 32bit addr space. */
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static void mmubooke_create_initial_mapping(CPUPPCState *env,
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target_ulong va,
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hwaddr pa)
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{
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ppcemb_tlb_t *tlb = &env->tlb.tlbe[0];
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tlb->attr = 0;
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tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4);
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tlb->size = 1 << 31; /* up to 0x80000000 */
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tlb->EPN = va & TARGET_PAGE_MASK;
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tlb->RPN = pa & TARGET_PAGE_MASK;
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tlb->PID = 0;
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}
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static void main_cpu_reset(void *opaque)
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{
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PowerPCCPU *cpu = opaque;
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CPUPPCState *env = &cpu->env;
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struct boot_info *bi = env->load_info;
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cpu_reset(CPU(cpu));
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/* either we have a kernel to boot or we jump to U-Boot */
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if (bi->entry != UBOOT_ENTRY) {
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env->gpr[1] = (16 * MiB) - 8;
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env->gpr[3] = FDT_ADDR;
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env->nip = bi->entry;
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/* Create a mapping for the kernel. */
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mmubooke_create_initial_mapping(env, 0, 0);
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env->gpr[6] = tswap32(EPAPR_MAGIC);
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env->gpr[7] = (16 * MiB) - 8; /* bi->ima_size; */
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} else {
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env->nip = UBOOT_ENTRY;
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mmubooke_create_initial_mapping_uboot(env);
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}
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}
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static void sam460ex_init(MachineState *machine)
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{
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MemoryRegion *address_space_mem = get_system_memory();
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MemoryRegion *isa = g_new(MemoryRegion, 1);
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MemoryRegion *ram_memories = g_new(MemoryRegion, SDRAM_NR_BANKS);
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hwaddr ram_bases[SDRAM_NR_BANKS] = {0};
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hwaddr ram_sizes[SDRAM_NR_BANKS] = {0};
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MemoryRegion *l2cache_ram = g_new(MemoryRegion, 1);
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qemu_irq *irqs, *uic[4];
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PCIBus *pci_bus;
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PowerPCCPU *cpu;
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CPUPPCState *env;
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I2CBus *i2c;
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hwaddr entry = UBOOT_ENTRY;
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hwaddr loadaddr = LOAD_UIMAGE_LOADADDR_INVALID;
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target_long initrd_size = 0;
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DeviceState *dev;
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SysBusDevice *sbdev;
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struct boot_info *boot_info;
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uint8_t *spd_data;
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Error *err = NULL;
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int success;
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cpu = POWERPC_CPU(cpu_create(machine->cpu_type));
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env = &cpu->env;
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if (env->mmu_model != POWERPC_MMU_BOOKE) {
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error_report("Only MMU model BookE is supported by this machine.");
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exit(1);
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}
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qemu_register_reset(main_cpu_reset, cpu);
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boot_info = g_malloc0(sizeof(*boot_info));
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env->load_info = boot_info;
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ppc_booke_timers_init(cpu, CPU_FREQ, 0);
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ppc_dcr_init(env, NULL, NULL);
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/* PLB arbitrer */
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ppc4xx_plb_init(env);
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/* interrupt controllers */
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irqs = g_new0(qemu_irq, PPCUIC_OUTPUT_NB);
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irqs[PPCUIC_OUTPUT_INT] = ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT];
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irqs[PPCUIC_OUTPUT_CINT] = ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT];
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uic[0] = ppcuic_init(env, irqs, 0xc0, 0, 1);
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uic[1] = ppcuic_init(env, &uic[0][30], 0xd0, 0, 1);
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uic[2] = ppcuic_init(env, &uic[0][10], 0xe0, 0, 1);
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uic[3] = ppcuic_init(env, &uic[0][16], 0xf0, 0, 1);
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/* SDRAM controller */
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/* put all RAM on first bank because board has one slot
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* and firmware only checks that */
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machine->ram_size = ppc4xx_sdram_adjust(machine->ram_size, 1,
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ram_memories, ram_bases, ram_sizes,
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ppc460ex_sdram_bank_sizes);
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/* FIXME: does 460EX have ECC interrupts? */
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ppc440_sdram_init(env, SDRAM_NR_BANKS, ram_memories,
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ram_bases, ram_sizes, 1);
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/* IIC controllers and devices */
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dev = sysbus_create_simple(TYPE_PPC4xx_I2C, 0x4ef600700, uic[0][2]);
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i2c = PPC4xx_I2C(dev)->bus;
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/* SPD EEPROM on RAM module */
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spd_data = spd_data_generate(DDR2, ram_sizes[0], &err);
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if (err) {
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warn_report_err(err);
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}
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if (spd_data) {
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spd_data[20] = 4; /* SO-DIMM module */
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smbus_eeprom_init_one(i2c, 0x50, spd_data);
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}
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/* RTC */
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i2c_create_slave(i2c, "m41t80", 0x68);
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dev = sysbus_create_simple(TYPE_PPC4xx_I2C, 0x4ef600800, uic[0][3]);
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/* External bus controller */
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ppc405_ebc_init(env);
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/* CPR */
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ppc4xx_cpr_init(env);
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/* PLB to AHB bridge */
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ppc4xx_ahb_init(env);
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/* System DCRs */
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ppc4xx_sdr_init(env);
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/* MAL */
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ppc4xx_mal_init(env, 4, 16, &uic[2][3]);
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/* DMA */
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ppc4xx_dma_init(env, 0x200);
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/* 256K of L2 cache as memory */
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ppc4xx_l2sram_init(env);
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/* FIXME: remove this after fixing l2sram mapping in ppc440_uc.c? */
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memory_region_init_ram(l2cache_ram, NULL, "ppc440.l2cache_ram", 256 * KiB,
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&error_abort);
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memory_region_add_subregion(address_space_mem, 0x400000000LL, l2cache_ram);
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/* USB */
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sysbus_create_simple(TYPE_PPC4xx_EHCI, 0x4bffd0400, uic[2][29]);
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dev = qdev_create(NULL, "sysbus-ohci");
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qdev_prop_set_string(dev, "masterbus", "usb-bus.0");
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qdev_prop_set_uint32(dev, "num-ports", 6);
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qdev_init_nofail(dev);
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sbdev = SYS_BUS_DEVICE(dev);
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sysbus_mmio_map(sbdev, 0, 0x4bffd0000);
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sysbus_connect_irq(sbdev, 0, uic[2][30]);
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usb_create_simple(usb_bus_find(-1), "usb-kbd");
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usb_create_simple(usb_bus_find(-1), "usb-mouse");
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/* PCI bus */
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ppc460ex_pcie_init(env);
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/* All PCI irqs are connected to the same UIC pin (cf. UBoot source) */
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dev = sysbus_create_simple("ppc440-pcix-host", 0xc0ec00000, uic[1][0]);
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pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci.0");
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if (!pci_bus) {
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error_report("couldn't create PCI controller!");
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exit(1);
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}
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memory_region_init_alias(isa, NULL, "isa_mmio", get_system_io(),
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0, 0x10000);
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memory_region_add_subregion(get_system_memory(), 0xc08000000, isa);
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/* PCI devices */
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pci_create_simple(pci_bus, PCI_DEVFN(6, 0), "sm501");
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/* SoC has a single SATA port but we don't emulate that yet
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* However, firmware and usual clients have driver for SiI311x
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* so add one for convenience by default */
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if (defaults_enabled()) {
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pci_create_simple(pci_bus, -1, "sii3112");
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}
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/* SoC has 4 UARTs
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* but board has only one wired and two are present in fdt */
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if (serial_hd(0) != NULL) {
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serial_mm_init(address_space_mem, 0x4ef600300, 0, uic[1][1],
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PPC_SERIAL_MM_BAUDBASE, serial_hd(0),
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DEVICE_BIG_ENDIAN);
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}
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if (serial_hd(1) != NULL) {
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serial_mm_init(address_space_mem, 0x4ef600400, 0, uic[0][1],
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PPC_SERIAL_MM_BAUDBASE, serial_hd(1),
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DEVICE_BIG_ENDIAN);
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}
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/* Load U-Boot image. */
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if (!machine->kernel_filename) {
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success = sam460ex_load_uboot();
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if (success < 0) {
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error_report("could not load firmware");
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exit(1);
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}
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}
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/* Load kernel. */
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if (machine->kernel_filename) {
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success = load_uimage(machine->kernel_filename, &entry, &loadaddr,
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NULL, NULL, NULL);
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if (success < 0) {
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uint64_t elf_entry, elf_lowaddr;
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success = load_elf(machine->kernel_filename, NULL, NULL, &elf_entry,
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&elf_lowaddr, NULL, 1, PPC_ELF_MACHINE, 0, 0);
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entry = elf_entry;
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loadaddr = elf_lowaddr;
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}
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/* XXX try again as binary */
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if (success < 0) {
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error_report("could not load kernel '%s'",
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machine->kernel_filename);
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exit(1);
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}
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}
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/* Load initrd. */
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if (machine->initrd_filename) {
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initrd_size = load_image_targphys(machine->initrd_filename,
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RAMDISK_ADDR,
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machine->ram_size - RAMDISK_ADDR);
|
|
if (initrd_size < 0) {
|
|
error_report("could not load ram disk '%s' at %x",
|
|
machine->initrd_filename, RAMDISK_ADDR);
|
|
exit(1);
|
|
}
|
|
}
|
|
|
|
/* If we're loading a kernel directly, we must load the device tree too. */
|
|
if (machine->kernel_filename) {
|
|
int dt_size;
|
|
|
|
dt_size = sam460ex_load_device_tree(FDT_ADDR, machine->ram_size,
|
|
RAMDISK_ADDR, initrd_size,
|
|
machine->kernel_cmdline);
|
|
|
|
boot_info->dt_base = FDT_ADDR;
|
|
boot_info->dt_size = dt_size;
|
|
}
|
|
|
|
boot_info->entry = entry;
|
|
}
|
|
|
|
static void sam460ex_machine_init(MachineClass *mc)
|
|
{
|
|
mc->desc = "aCube Sam460ex";
|
|
mc->init = sam460ex_init;
|
|
mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("460exb");
|
|
mc->default_ram_size = 512 * MiB;
|
|
}
|
|
|
|
DEFINE_MACHINE("sam460ex", sam460ex_machine_init)
|