70f168f88c
Move a use of TARGET_LONG_BITS out of tcg/tcg.h. Include the new file only where required. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
476 lines
18 KiB
C
476 lines
18 KiB
C
/*
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* Software MMU support
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*
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*/
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/*
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* Generate inline load/store functions for all MMU modes (typically
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* at least _user and _kernel) as well as _data versions, for all data
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* sizes.
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*
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* Used by target op helpers.
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*
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* The syntax for the accessors is:
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*
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* load: cpu_ld{sign}{size}{end}_{mmusuffix}(env, ptr)
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* cpu_ld{sign}{size}{end}_{mmusuffix}_ra(env, ptr, retaddr)
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* cpu_ld{sign}{size}{end}_mmuidx_ra(env, ptr, mmu_idx, retaddr)
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* cpu_ld{sign}{size}{end}_mmu(env, ptr, oi, retaddr)
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*
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* store: cpu_st{size}{end}_{mmusuffix}(env, ptr, val)
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* cpu_st{size}{end}_{mmusuffix}_ra(env, ptr, val, retaddr)
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* cpu_st{size}{end}_mmuidx_ra(env, ptr, val, mmu_idx, retaddr)
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* cpu_st{size}{end}_mmu(env, ptr, val, oi, retaddr)
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*
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* sign is:
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* (empty): for 32 and 64 bit sizes
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* u : unsigned
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* s : signed
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*
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* size is:
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* b: 8 bits
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* w: 16 bits
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* l: 32 bits
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* q: 64 bits
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*
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* end is:
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* (empty): for target native endian, or for 8 bit access
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* _be: for forced big endian
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* _le: for forced little endian
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*
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* mmusuffix is one of the generic suffixes "data" or "code", or "mmuidx".
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* The "mmuidx" suffix carries an extra mmu_idx argument that specifies
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* the index to use; the "data" and "code" suffixes take the index from
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* cpu_mmu_index().
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*
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* The "mmu" suffix carries the full MemOpIdx, with both mmu_idx and the
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* MemOp including alignment requirements. The alignment will be enforced.
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*/
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#ifndef CPU_LDST_H
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#define CPU_LDST_H
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#include "exec/memopidx.h"
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#include "qemu/int128.h"
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#include "cpu.h"
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#if defined(CONFIG_USER_ONLY)
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/* sparc32plus has 64bit long but 32bit space address
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* this can make bad result with g2h() and h2g()
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*/
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#if TARGET_VIRT_ADDR_SPACE_BITS <= 32
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typedef uint32_t abi_ptr;
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#define TARGET_ABI_FMT_ptr "%x"
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#else
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typedef uint64_t abi_ptr;
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#define TARGET_ABI_FMT_ptr "%"PRIx64
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#endif
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#ifndef TARGET_TAGGED_ADDRESSES
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static inline abi_ptr cpu_untagged_addr(CPUState *cs, abi_ptr x)
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{
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return x;
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}
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#endif
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/* All direct uses of g2h and h2g need to go away for usermode softmmu. */
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static inline void *g2h_untagged(abi_ptr x)
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{
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return (void *)((uintptr_t)(x) + guest_base);
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}
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static inline void *g2h(CPUState *cs, abi_ptr x)
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{
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return g2h_untagged(cpu_untagged_addr(cs, x));
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}
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static inline bool guest_addr_valid_untagged(abi_ulong x)
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{
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return x <= GUEST_ADDR_MAX;
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}
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static inline bool guest_range_valid_untagged(abi_ulong start, abi_ulong len)
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{
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return len - 1 <= GUEST_ADDR_MAX && start <= GUEST_ADDR_MAX - len + 1;
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}
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#define h2g_valid(x) \
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(HOST_LONG_BITS <= TARGET_VIRT_ADDR_SPACE_BITS || \
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(uintptr_t)(x) - guest_base <= GUEST_ADDR_MAX)
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#define h2g_nocheck(x) ({ \
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uintptr_t __ret = (uintptr_t)(x) - guest_base; \
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(abi_ptr)__ret; \
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})
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#define h2g(x) ({ \
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/* Check if given address fits target address space */ \
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assert(h2g_valid(x)); \
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h2g_nocheck(x); \
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})
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#else
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typedef target_ulong abi_ptr;
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#define TARGET_ABI_FMT_ptr TARGET_FMT_lx
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#endif
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uint32_t cpu_ldub_data(CPUArchState *env, abi_ptr ptr);
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int cpu_ldsb_data(CPUArchState *env, abi_ptr ptr);
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uint32_t cpu_lduw_be_data(CPUArchState *env, abi_ptr ptr);
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int cpu_ldsw_be_data(CPUArchState *env, abi_ptr ptr);
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uint32_t cpu_ldl_be_data(CPUArchState *env, abi_ptr ptr);
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uint64_t cpu_ldq_be_data(CPUArchState *env, abi_ptr ptr);
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uint32_t cpu_lduw_le_data(CPUArchState *env, abi_ptr ptr);
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int cpu_ldsw_le_data(CPUArchState *env, abi_ptr ptr);
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uint32_t cpu_ldl_le_data(CPUArchState *env, abi_ptr ptr);
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uint64_t cpu_ldq_le_data(CPUArchState *env, abi_ptr ptr);
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uint32_t cpu_ldub_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
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int cpu_ldsb_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
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uint32_t cpu_lduw_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
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int cpu_ldsw_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
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uint32_t cpu_ldl_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
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uint64_t cpu_ldq_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
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uint32_t cpu_lduw_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
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int cpu_ldsw_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
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uint32_t cpu_ldl_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
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uint64_t cpu_ldq_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
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void cpu_stb_data(CPUArchState *env, abi_ptr ptr, uint32_t val);
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void cpu_stw_be_data(CPUArchState *env, abi_ptr ptr, uint32_t val);
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void cpu_stl_be_data(CPUArchState *env, abi_ptr ptr, uint32_t val);
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void cpu_stq_be_data(CPUArchState *env, abi_ptr ptr, uint64_t val);
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void cpu_stw_le_data(CPUArchState *env, abi_ptr ptr, uint32_t val);
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void cpu_stl_le_data(CPUArchState *env, abi_ptr ptr, uint32_t val);
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void cpu_stq_le_data(CPUArchState *env, abi_ptr ptr, uint64_t val);
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void cpu_stb_data_ra(CPUArchState *env, abi_ptr ptr,
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uint32_t val, uintptr_t ra);
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void cpu_stw_be_data_ra(CPUArchState *env, abi_ptr ptr,
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uint32_t val, uintptr_t ra);
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void cpu_stl_be_data_ra(CPUArchState *env, abi_ptr ptr,
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uint32_t val, uintptr_t ra);
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void cpu_stq_be_data_ra(CPUArchState *env, abi_ptr ptr,
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uint64_t val, uintptr_t ra);
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void cpu_stw_le_data_ra(CPUArchState *env, abi_ptr ptr,
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uint32_t val, uintptr_t ra);
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void cpu_stl_le_data_ra(CPUArchState *env, abi_ptr ptr,
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uint32_t val, uintptr_t ra);
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void cpu_stq_le_data_ra(CPUArchState *env, abi_ptr ptr,
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uint64_t val, uintptr_t ra);
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uint32_t cpu_ldub_mmuidx_ra(CPUArchState *env, abi_ptr ptr,
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int mmu_idx, uintptr_t ra);
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int cpu_ldsb_mmuidx_ra(CPUArchState *env, abi_ptr ptr,
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int mmu_idx, uintptr_t ra);
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uint32_t cpu_lduw_be_mmuidx_ra(CPUArchState *env, abi_ptr ptr,
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int mmu_idx, uintptr_t ra);
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int cpu_ldsw_be_mmuidx_ra(CPUArchState *env, abi_ptr ptr,
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int mmu_idx, uintptr_t ra);
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uint32_t cpu_ldl_be_mmuidx_ra(CPUArchState *env, abi_ptr ptr,
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int mmu_idx, uintptr_t ra);
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uint64_t cpu_ldq_be_mmuidx_ra(CPUArchState *env, abi_ptr ptr,
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int mmu_idx, uintptr_t ra);
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uint32_t cpu_lduw_le_mmuidx_ra(CPUArchState *env, abi_ptr ptr,
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int mmu_idx, uintptr_t ra);
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int cpu_ldsw_le_mmuidx_ra(CPUArchState *env, abi_ptr ptr,
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int mmu_idx, uintptr_t ra);
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uint32_t cpu_ldl_le_mmuidx_ra(CPUArchState *env, abi_ptr ptr,
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int mmu_idx, uintptr_t ra);
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uint64_t cpu_ldq_le_mmuidx_ra(CPUArchState *env, abi_ptr ptr,
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int mmu_idx, uintptr_t ra);
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void cpu_stb_mmuidx_ra(CPUArchState *env, abi_ptr ptr, uint32_t val,
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int mmu_idx, uintptr_t ra);
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void cpu_stw_be_mmuidx_ra(CPUArchState *env, abi_ptr ptr, uint32_t val,
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int mmu_idx, uintptr_t ra);
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void cpu_stl_be_mmuidx_ra(CPUArchState *env, abi_ptr ptr, uint32_t val,
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int mmu_idx, uintptr_t ra);
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void cpu_stq_be_mmuidx_ra(CPUArchState *env, abi_ptr ptr, uint64_t val,
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int mmu_idx, uintptr_t ra);
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void cpu_stw_le_mmuidx_ra(CPUArchState *env, abi_ptr ptr, uint32_t val,
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int mmu_idx, uintptr_t ra);
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void cpu_stl_le_mmuidx_ra(CPUArchState *env, abi_ptr ptr, uint32_t val,
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int mmu_idx, uintptr_t ra);
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void cpu_stq_le_mmuidx_ra(CPUArchState *env, abi_ptr ptr, uint64_t val,
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int mmu_idx, uintptr_t ra);
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uint8_t cpu_ldb_mmu(CPUArchState *env, abi_ptr ptr, MemOpIdx oi, uintptr_t ra);
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uint16_t cpu_ldw_mmu(CPUArchState *env, abi_ptr ptr, MemOpIdx oi, uintptr_t ra);
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uint32_t cpu_ldl_mmu(CPUArchState *env, abi_ptr ptr, MemOpIdx oi, uintptr_t ra);
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uint64_t cpu_ldq_mmu(CPUArchState *env, abi_ptr ptr, MemOpIdx oi, uintptr_t ra);
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Int128 cpu_ld16_mmu(CPUArchState *env, abi_ptr addr, MemOpIdx oi, uintptr_t ra);
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void cpu_stb_mmu(CPUArchState *env, abi_ptr ptr, uint8_t val,
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MemOpIdx oi, uintptr_t ra);
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void cpu_stw_mmu(CPUArchState *env, abi_ptr ptr, uint16_t val,
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MemOpIdx oi, uintptr_t ra);
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void cpu_stl_mmu(CPUArchState *env, abi_ptr ptr, uint32_t val,
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MemOpIdx oi, uintptr_t ra);
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void cpu_stq_mmu(CPUArchState *env, abi_ptr ptr, uint64_t val,
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MemOpIdx oi, uintptr_t ra);
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void cpu_st16_mmu(CPUArchState *env, abi_ptr addr, Int128 val,
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MemOpIdx oi, uintptr_t ra);
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uint32_t cpu_atomic_cmpxchgb_mmu(CPUArchState *env, target_ulong addr,
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uint32_t cmpv, uint32_t newv,
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MemOpIdx oi, uintptr_t retaddr);
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uint32_t cpu_atomic_cmpxchgw_le_mmu(CPUArchState *env, target_ulong addr,
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uint32_t cmpv, uint32_t newv,
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MemOpIdx oi, uintptr_t retaddr);
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uint32_t cpu_atomic_cmpxchgl_le_mmu(CPUArchState *env, target_ulong addr,
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uint32_t cmpv, uint32_t newv,
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MemOpIdx oi, uintptr_t retaddr);
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uint64_t cpu_atomic_cmpxchgq_le_mmu(CPUArchState *env, target_ulong addr,
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uint64_t cmpv, uint64_t newv,
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MemOpIdx oi, uintptr_t retaddr);
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uint32_t cpu_atomic_cmpxchgw_be_mmu(CPUArchState *env, target_ulong addr,
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uint32_t cmpv, uint32_t newv,
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MemOpIdx oi, uintptr_t retaddr);
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uint32_t cpu_atomic_cmpxchgl_be_mmu(CPUArchState *env, target_ulong addr,
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uint32_t cmpv, uint32_t newv,
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MemOpIdx oi, uintptr_t retaddr);
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uint64_t cpu_atomic_cmpxchgq_be_mmu(CPUArchState *env, target_ulong addr,
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uint64_t cmpv, uint64_t newv,
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MemOpIdx oi, uintptr_t retaddr);
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#define GEN_ATOMIC_HELPER(NAME, TYPE, SUFFIX) \
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TYPE cpu_atomic_ ## NAME ## SUFFIX ## _mmu \
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(CPUArchState *env, target_ulong addr, TYPE val, \
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MemOpIdx oi, uintptr_t retaddr);
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#ifdef CONFIG_ATOMIC64
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#define GEN_ATOMIC_HELPER_ALL(NAME) \
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GEN_ATOMIC_HELPER(NAME, uint32_t, b) \
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GEN_ATOMIC_HELPER(NAME, uint32_t, w_le) \
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GEN_ATOMIC_HELPER(NAME, uint32_t, w_be) \
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GEN_ATOMIC_HELPER(NAME, uint32_t, l_le) \
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GEN_ATOMIC_HELPER(NAME, uint32_t, l_be) \
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GEN_ATOMIC_HELPER(NAME, uint64_t, q_le) \
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GEN_ATOMIC_HELPER(NAME, uint64_t, q_be)
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#else
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#define GEN_ATOMIC_HELPER_ALL(NAME) \
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GEN_ATOMIC_HELPER(NAME, uint32_t, b) \
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GEN_ATOMIC_HELPER(NAME, uint32_t, w_le) \
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GEN_ATOMIC_HELPER(NAME, uint32_t, w_be) \
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GEN_ATOMIC_HELPER(NAME, uint32_t, l_le) \
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GEN_ATOMIC_HELPER(NAME, uint32_t, l_be)
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#endif
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GEN_ATOMIC_HELPER_ALL(fetch_add)
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GEN_ATOMIC_HELPER_ALL(fetch_sub)
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GEN_ATOMIC_HELPER_ALL(fetch_and)
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GEN_ATOMIC_HELPER_ALL(fetch_or)
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GEN_ATOMIC_HELPER_ALL(fetch_xor)
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GEN_ATOMIC_HELPER_ALL(fetch_smin)
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GEN_ATOMIC_HELPER_ALL(fetch_umin)
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GEN_ATOMIC_HELPER_ALL(fetch_smax)
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GEN_ATOMIC_HELPER_ALL(fetch_umax)
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GEN_ATOMIC_HELPER_ALL(add_fetch)
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GEN_ATOMIC_HELPER_ALL(sub_fetch)
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GEN_ATOMIC_HELPER_ALL(and_fetch)
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GEN_ATOMIC_HELPER_ALL(or_fetch)
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GEN_ATOMIC_HELPER_ALL(xor_fetch)
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GEN_ATOMIC_HELPER_ALL(smin_fetch)
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GEN_ATOMIC_HELPER_ALL(umin_fetch)
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GEN_ATOMIC_HELPER_ALL(smax_fetch)
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GEN_ATOMIC_HELPER_ALL(umax_fetch)
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GEN_ATOMIC_HELPER_ALL(xchg)
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#undef GEN_ATOMIC_HELPER_ALL
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#undef GEN_ATOMIC_HELPER
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Int128 cpu_atomic_cmpxchgo_le_mmu(CPUArchState *env, target_ulong addr,
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Int128 cmpv, Int128 newv,
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MemOpIdx oi, uintptr_t retaddr);
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Int128 cpu_atomic_cmpxchgo_be_mmu(CPUArchState *env, target_ulong addr,
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Int128 cmpv, Int128 newv,
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MemOpIdx oi, uintptr_t retaddr);
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#if defined(CONFIG_USER_ONLY)
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extern __thread uintptr_t helper_retaddr;
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static inline void set_helper_retaddr(uintptr_t ra)
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{
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helper_retaddr = ra;
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/*
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* Ensure that this write is visible to the SIGSEGV handler that
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* may be invoked due to a subsequent invalid memory operation.
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*/
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signal_barrier();
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}
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static inline void clear_helper_retaddr(void)
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{
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/*
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* Ensure that previous memory operations have succeeded before
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* removing the data visible to the signal handler.
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*/
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signal_barrier();
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helper_retaddr = 0;
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}
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#else
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#include "tcg/oversized-guest.h"
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static inline target_ulong tlb_read_idx(const CPUTLBEntry *entry,
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MMUAccessType access_type)
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{
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/* Do not rearrange the CPUTLBEntry structure members. */
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QEMU_BUILD_BUG_ON(offsetof(CPUTLBEntry, addr_read) !=
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MMU_DATA_LOAD * sizeof(uint64_t));
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QEMU_BUILD_BUG_ON(offsetof(CPUTLBEntry, addr_write) !=
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MMU_DATA_STORE * sizeof(uint64_t));
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QEMU_BUILD_BUG_ON(offsetof(CPUTLBEntry, addr_code) !=
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MMU_INST_FETCH * sizeof(uint64_t));
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#if TARGET_LONG_BITS == 32
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/* Use qatomic_read, in case of addr_write; only care about low bits. */
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const uint32_t *ptr = (uint32_t *)&entry->addr_idx[access_type];
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ptr += HOST_BIG_ENDIAN;
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return qatomic_read(ptr);
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#else
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const uint64_t *ptr = &entry->addr_idx[access_type];
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# if TCG_OVERSIZED_GUEST
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return *ptr;
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# else
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/* ofs might correspond to .addr_write, so use qatomic_read */
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return qatomic_read(ptr);
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# endif
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#endif
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}
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static inline target_ulong tlb_addr_write(const CPUTLBEntry *entry)
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{
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return tlb_read_idx(entry, MMU_DATA_STORE);
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}
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/* Find the TLB index corresponding to the mmu_idx + address pair. */
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static inline uintptr_t tlb_index(CPUArchState *env, uintptr_t mmu_idx,
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target_ulong addr)
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{
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uintptr_t size_mask = env_tlb(env)->f[mmu_idx].mask >> CPU_TLB_ENTRY_BITS;
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return (addr >> TARGET_PAGE_BITS) & size_mask;
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}
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/* Find the TLB entry corresponding to the mmu_idx + address pair. */
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static inline CPUTLBEntry *tlb_entry(CPUArchState *env, uintptr_t mmu_idx,
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target_ulong addr)
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{
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return &env_tlb(env)->f[mmu_idx].table[tlb_index(env, mmu_idx, addr)];
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}
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#endif /* defined(CONFIG_USER_ONLY) */
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#if TARGET_BIG_ENDIAN
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# define cpu_lduw_data cpu_lduw_be_data
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# define cpu_ldsw_data cpu_ldsw_be_data
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# define cpu_ldl_data cpu_ldl_be_data
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# define cpu_ldq_data cpu_ldq_be_data
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# define cpu_lduw_data_ra cpu_lduw_be_data_ra
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# define cpu_ldsw_data_ra cpu_ldsw_be_data_ra
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# define cpu_ldl_data_ra cpu_ldl_be_data_ra
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# define cpu_ldq_data_ra cpu_ldq_be_data_ra
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# define cpu_lduw_mmuidx_ra cpu_lduw_be_mmuidx_ra
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# define cpu_ldsw_mmuidx_ra cpu_ldsw_be_mmuidx_ra
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# define cpu_ldl_mmuidx_ra cpu_ldl_be_mmuidx_ra
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# define cpu_ldq_mmuidx_ra cpu_ldq_be_mmuidx_ra
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# define cpu_stw_data cpu_stw_be_data
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# define cpu_stl_data cpu_stl_be_data
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# define cpu_stq_data cpu_stq_be_data
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# define cpu_stw_data_ra cpu_stw_be_data_ra
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# define cpu_stl_data_ra cpu_stl_be_data_ra
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# define cpu_stq_data_ra cpu_stq_be_data_ra
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# define cpu_stw_mmuidx_ra cpu_stw_be_mmuidx_ra
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# define cpu_stl_mmuidx_ra cpu_stl_be_mmuidx_ra
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# define cpu_stq_mmuidx_ra cpu_stq_be_mmuidx_ra
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#else
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# define cpu_lduw_data cpu_lduw_le_data
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# define cpu_ldsw_data cpu_ldsw_le_data
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# define cpu_ldl_data cpu_ldl_le_data
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# define cpu_ldq_data cpu_ldq_le_data
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# define cpu_lduw_data_ra cpu_lduw_le_data_ra
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# define cpu_ldsw_data_ra cpu_ldsw_le_data_ra
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# define cpu_ldl_data_ra cpu_ldl_le_data_ra
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# define cpu_ldq_data_ra cpu_ldq_le_data_ra
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# define cpu_lduw_mmuidx_ra cpu_lduw_le_mmuidx_ra
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# define cpu_ldsw_mmuidx_ra cpu_ldsw_le_mmuidx_ra
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# define cpu_ldl_mmuidx_ra cpu_ldl_le_mmuidx_ra
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# define cpu_ldq_mmuidx_ra cpu_ldq_le_mmuidx_ra
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# define cpu_stw_data cpu_stw_le_data
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# define cpu_stl_data cpu_stl_le_data
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# define cpu_stq_data cpu_stq_le_data
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# define cpu_stw_data_ra cpu_stw_le_data_ra
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# define cpu_stl_data_ra cpu_stl_le_data_ra
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# define cpu_stq_data_ra cpu_stq_le_data_ra
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# define cpu_stw_mmuidx_ra cpu_stw_le_mmuidx_ra
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# define cpu_stl_mmuidx_ra cpu_stl_le_mmuidx_ra
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# define cpu_stq_mmuidx_ra cpu_stq_le_mmuidx_ra
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#endif
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uint8_t cpu_ldb_code_mmu(CPUArchState *env, abi_ptr addr,
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MemOpIdx oi, uintptr_t ra);
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uint16_t cpu_ldw_code_mmu(CPUArchState *env, abi_ptr addr,
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MemOpIdx oi, uintptr_t ra);
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uint32_t cpu_ldl_code_mmu(CPUArchState *env, abi_ptr addr,
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MemOpIdx oi, uintptr_t ra);
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uint64_t cpu_ldq_code_mmu(CPUArchState *env, abi_ptr addr,
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MemOpIdx oi, uintptr_t ra);
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uint32_t cpu_ldub_code(CPUArchState *env, abi_ptr addr);
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uint32_t cpu_lduw_code(CPUArchState *env, abi_ptr addr);
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uint32_t cpu_ldl_code(CPUArchState *env, abi_ptr addr);
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uint64_t cpu_ldq_code(CPUArchState *env, abi_ptr addr);
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static inline int cpu_ldsb_code(CPUArchState *env, abi_ptr addr)
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{
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return (int8_t)cpu_ldub_code(env, addr);
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}
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static inline int cpu_ldsw_code(CPUArchState *env, abi_ptr addr)
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{
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return (int16_t)cpu_lduw_code(env, addr);
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}
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/**
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* tlb_vaddr_to_host:
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* @env: CPUArchState
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* @addr: guest virtual address to look up
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* @access_type: 0 for read, 1 for write, 2 for execute
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* @mmu_idx: MMU index to use for lookup
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*
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* Look up the specified guest virtual index in the TCG softmmu TLB.
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* If we can translate a host virtual address suitable for direct RAM
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* access, without causing a guest exception, then return it.
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* Otherwise (TLB entry is for an I/O access, guest software
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* TLB fill required, etc) return NULL.
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*/
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#ifdef CONFIG_USER_ONLY
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static inline void *tlb_vaddr_to_host(CPUArchState *env, abi_ptr addr,
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MMUAccessType access_type, int mmu_idx)
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{
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return g2h(env_cpu(env), addr);
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}
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#else
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void *tlb_vaddr_to_host(CPUArchState *env, abi_ptr addr,
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MMUAccessType access_type, int mmu_idx);
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#endif
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#endif /* CPU_LDST_H */
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