ba1ba5cca3
there are 2 use cases to deal with:
1: fixed CPU models per board/soc
2: boards with user configurable cpu_model and fallback to
default cpu_model if user hasn't specified one explicitly
For the 1st
drop intermediate cpu_model parsing and use const cpu type
directly, which replaces:
typename = object_class_get_name(
cpu_class_by_name(TYPE_ARM_CPU, cpu_model))
object_new(typename)
with
object_new(FOO_CPU_TYPE_NAME)
or
cpu_generic_init(BASE_CPU_TYPE, "my cpu model")
with
cpu_create(FOO_CPU_TYPE_NAME)
as result 1st use case doesn't have to invoke not necessary
translation and not needed code is removed.
For the 2nd
1: set default cpu type with MachineClass::default_cpu_type and
2: use generic cpu_model parsing that done before machine_init()
is run and:
2.1: drop custom cpu_model parsing where pattern is:
typename = object_class_get_name(
cpu_class_by_name(TYPE_ARM_CPU, cpu_model))
[parse_features(typename, cpu_model, &err) ]
2.2: or replace cpu_generic_init() which does what
2.1 does + create_cpu(typename) with just
create_cpu(machine->cpu_type)
as result cpu_name -> cpu_type translation is done using
generic machine code one including parsing optional features
if supported/present (removes a bunch of duplicated cpu_model
parsing code) and default cpu type is defined in an uniform way
within machine_class_init callbacks instead of adhoc places
in boadr's machine_init code.
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Eduardo Habkost <ehabkost@redhat.com>
Message-Id: <1505318697-77161-6-git-send-email-imammedo@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
229 lines
8.2 KiB
C
229 lines
8.2 KiB
C
/*
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* STM32F205 SoC
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*
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* Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "qemu-common.h"
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#include "hw/arm/arm.h"
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#include "exec/address-spaces.h"
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#include "hw/arm/stm32f205_soc.h"
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/* At the moment only Timer 2 to 5 are modelled */
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static const uint32_t timer_addr[STM_NUM_TIMERS] = { 0x40000000, 0x40000400,
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0x40000800, 0x40000C00 };
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static const uint32_t usart_addr[STM_NUM_USARTS] = { 0x40011000, 0x40004400,
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0x40004800, 0x40004C00, 0x40005000, 0x40011400 };
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static const uint32_t adc_addr[STM_NUM_ADCS] = { 0x40012000, 0x40012100,
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0x40012200 };
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static const uint32_t spi_addr[STM_NUM_SPIS] = { 0x40013000, 0x40003800,
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0x40003C00 };
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static const int timer_irq[STM_NUM_TIMERS] = {28, 29, 30, 50};
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static const int usart_irq[STM_NUM_USARTS] = {37, 38, 39, 52, 53, 71};
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#define ADC_IRQ 18
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static const int spi_irq[STM_NUM_SPIS] = {35, 36, 51};
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static void stm32f205_soc_initfn(Object *obj)
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{
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STM32F205State *s = STM32F205_SOC(obj);
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int i;
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object_initialize(&s->armv7m, sizeof(s->armv7m), TYPE_ARMV7M);
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qdev_set_parent_bus(DEVICE(&s->armv7m), sysbus_get_default());
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object_initialize(&s->syscfg, sizeof(s->syscfg), TYPE_STM32F2XX_SYSCFG);
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qdev_set_parent_bus(DEVICE(&s->syscfg), sysbus_get_default());
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for (i = 0; i < STM_NUM_USARTS; i++) {
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object_initialize(&s->usart[i], sizeof(s->usart[i]),
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TYPE_STM32F2XX_USART);
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qdev_set_parent_bus(DEVICE(&s->usart[i]), sysbus_get_default());
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}
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for (i = 0; i < STM_NUM_TIMERS; i++) {
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object_initialize(&s->timer[i], sizeof(s->timer[i]),
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TYPE_STM32F2XX_TIMER);
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qdev_set_parent_bus(DEVICE(&s->timer[i]), sysbus_get_default());
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}
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s->adc_irqs = OR_IRQ(object_new(TYPE_OR_IRQ));
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for (i = 0; i < STM_NUM_ADCS; i++) {
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object_initialize(&s->adc[i], sizeof(s->adc[i]),
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TYPE_STM32F2XX_ADC);
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qdev_set_parent_bus(DEVICE(&s->adc[i]), sysbus_get_default());
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}
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for (i = 0; i < STM_NUM_SPIS; i++) {
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object_initialize(&s->spi[i], sizeof(s->spi[i]),
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TYPE_STM32F2XX_SPI);
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qdev_set_parent_bus(DEVICE(&s->spi[i]), sysbus_get_default());
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}
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}
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static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
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{
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STM32F205State *s = STM32F205_SOC(dev_soc);
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DeviceState *dev, *armv7m;
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SysBusDevice *busdev;
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Error *err = NULL;
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int i;
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MemoryRegion *system_memory = get_system_memory();
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MemoryRegion *sram = g_new(MemoryRegion, 1);
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MemoryRegion *flash = g_new(MemoryRegion, 1);
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MemoryRegion *flash_alias = g_new(MemoryRegion, 1);
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memory_region_init_ram(flash, NULL, "STM32F205.flash", FLASH_SIZE,
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&error_fatal);
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memory_region_init_alias(flash_alias, NULL, "STM32F205.flash.alias",
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flash, 0, FLASH_SIZE);
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memory_region_set_readonly(flash, true);
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memory_region_set_readonly(flash_alias, true);
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memory_region_add_subregion(system_memory, FLASH_BASE_ADDRESS, flash);
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memory_region_add_subregion(system_memory, 0, flash_alias);
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memory_region_init_ram(sram, NULL, "STM32F205.sram", SRAM_SIZE,
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&error_fatal);
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memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram);
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armv7m = DEVICE(&s->armv7m);
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qdev_prop_set_uint32(armv7m, "num-irq", 96);
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qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type);
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object_property_set_link(OBJECT(&s->armv7m), OBJECT(get_system_memory()),
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"memory", &error_abort);
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object_property_set_bool(OBJECT(&s->armv7m), true, "realized", &err);
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if (err != NULL) {
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error_propagate(errp, err);
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return;
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}
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/* System configuration controller */
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dev = DEVICE(&s->syscfg);
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object_property_set_bool(OBJECT(&s->syscfg), true, "realized", &err);
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if (err != NULL) {
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error_propagate(errp, err);
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return;
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}
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busdev = SYS_BUS_DEVICE(dev);
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sysbus_mmio_map(busdev, 0, 0x40013800);
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sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, 71));
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/* Attach UART (uses USART registers) and USART controllers */
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for (i = 0; i < STM_NUM_USARTS; i++) {
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dev = DEVICE(&(s->usart[i]));
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qdev_prop_set_chr(dev, "chardev",
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i < MAX_SERIAL_PORTS ? serial_hds[i] : NULL);
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object_property_set_bool(OBJECT(&s->usart[i]), true, "realized", &err);
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if (err != NULL) {
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error_propagate(errp, err);
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return;
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}
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busdev = SYS_BUS_DEVICE(dev);
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sysbus_mmio_map(busdev, 0, usart_addr[i]);
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sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, usart_irq[i]));
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}
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/* Timer 2 to 5 */
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for (i = 0; i < STM_NUM_TIMERS; i++) {
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dev = DEVICE(&(s->timer[i]));
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qdev_prop_set_uint64(dev, "clock-frequency", 1000000000);
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object_property_set_bool(OBJECT(&s->timer[i]), true, "realized", &err);
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if (err != NULL) {
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error_propagate(errp, err);
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return;
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}
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busdev = SYS_BUS_DEVICE(dev);
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sysbus_mmio_map(busdev, 0, timer_addr[i]);
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sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, timer_irq[i]));
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}
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/* ADC 1 to 3 */
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object_property_set_int(OBJECT(s->adc_irqs), STM_NUM_ADCS,
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"num-lines", &err);
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object_property_set_bool(OBJECT(s->adc_irqs), true, "realized", &err);
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if (err != NULL) {
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error_propagate(errp, err);
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return;
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}
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qdev_connect_gpio_out(DEVICE(s->adc_irqs), 0,
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qdev_get_gpio_in(armv7m, ADC_IRQ));
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for (i = 0; i < STM_NUM_ADCS; i++) {
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dev = DEVICE(&(s->adc[i]));
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object_property_set_bool(OBJECT(&s->adc[i]), true, "realized", &err);
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if (err != NULL) {
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error_propagate(errp, err);
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return;
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}
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busdev = SYS_BUS_DEVICE(dev);
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sysbus_mmio_map(busdev, 0, adc_addr[i]);
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sysbus_connect_irq(busdev, 0,
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qdev_get_gpio_in(DEVICE(s->adc_irqs), i));
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}
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/* SPI 1 and 2 */
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for (i = 0; i < STM_NUM_SPIS; i++) {
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dev = DEVICE(&(s->spi[i]));
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object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err);
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if (err != NULL) {
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error_propagate(errp, err);
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return;
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}
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busdev = SYS_BUS_DEVICE(dev);
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sysbus_mmio_map(busdev, 0, spi_addr[i]);
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sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, spi_irq[i]));
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}
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}
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static Property stm32f205_soc_properties[] = {
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DEFINE_PROP_STRING("cpu-type", STM32F205State, cpu_type),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void stm32f205_soc_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->realize = stm32f205_soc_realize;
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dc->props = stm32f205_soc_properties;
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}
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static const TypeInfo stm32f205_soc_info = {
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.name = TYPE_STM32F205_SOC,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(STM32F205State),
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.instance_init = stm32f205_soc_initfn,
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.class_init = stm32f205_soc_class_init,
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};
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static void stm32f205_soc_types(void)
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{
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type_register_static(&stm32f205_soc_info);
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}
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type_init(stm32f205_soc_types)
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