7134cb07b7
Support all of the easy GM block sizes. Use direct memory operations, since the pointers are aligned. While BS=2 (16 bytes, 1 tag) is a legal setting, that requires an atomic store of one nibble. This is not difficult, but there is also no point in supporting it until required. Note that cortex-a710 sets GM blocksize to match its cacheline size of 64 bytes. I expect many implementations will also match the cacheline, which makes 16 bytes very unlikely. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20230811214031.171020-4-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
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.. | ||
hvf | ||
tcg | ||
arch_dump.c | ||
arm-powerctl.c | ||
arm-powerctl.h | ||
arm-qmp-cmds.c | ||
common-semi-target.h | ||
cortex-regs.c | ||
cpregs.h | ||
cpu64.c | ||
cpu-param.h | ||
cpu-qom.h | ||
cpu.c | ||
cpu.h | ||
debug_helper.c | ||
gdbstub64.c | ||
gdbstub.c | ||
helper.c | ||
helper.h | ||
hvf_arm.h | ||
hyp_gdbstub.c | ||
idau.h | ||
internals.h | ||
Kconfig | ||
kvm64.c | ||
kvm_arm.h | ||
kvm-consts.h | ||
kvm-stub.c | ||
kvm.c | ||
machine.c | ||
meson.build | ||
op_addsub.h | ||
ptw.c | ||
syndrome.h | ||
tcg-stubs.c | ||
trace-events | ||
trace.h | ||
vfp_helper.c |