qemu-e2k

History

Blue Swirl bccd9ec5f0 softmmu_header: pass CPUState to tlb_fill Pass CPUState pointer to tlb_fill() instead of architecture local cpu_single_env hacks. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>		2011-10-01 09:31:26 +00:00
..
cpu.h	Remove unused is_softmmu parameter from cpu_handle_mmu_fault	2011-08-07 09:32:01 +00:00
helper.c	Use glib memory allocation and free functions	2011-08-20 23:01:08 -05:00
helper.h	lm32: translation code helper	2011-03-07 13:42:36 +01:00
machine.c	lm32: machine state loading/saving	2011-03-07 13:42:36 +01:00
op_helper.c	softmmu_header: pass CPUState to tlb_fill	2011-10-01 09:31:26 +00:00
README	lm32: todo and documentation	2011-03-07 13:42:37 +01:00
TODO	lm32: todo and documentation	2011-03-07 13:42:37 +01:00
translate.c	Remove exec-all.h include directives	2011-06-26 18:25:35 +00:00

README

LatticeMico32 target
--------------------

General
-------
All opcodes including the JUART CSRs are supported.


JTAG UART
---------
JTAG UART is routed to a serial console device. For the current boards it
is the second one. Ie to enable it in the qemu virtual console window use
the following command line parameters:
  -serial vc -serial vc
This will make serial0 (the lm32_uart) and serial1 (the JTAG UART)
available as virtual consoles.


Programmatically terminate the emulator
----------------------------------------
Originally neither the LatticeMico32 nor its peripherals support a
mechanism to shut down the machine. Emulation aware programs can write to a
to a special register within the system control block to shut down the
virtual machine.  For more details see hw/lm32_sys.c. The lm32-evr is the
first BSP which instantiate this model. A (32 bit) write to 0xfff0000
causes a vm shutdown.


Special instructions
--------------------
The translation recognizes one special instruction to halt the cpu:
  and r0, r0, r0
On real hardware this instruction is a nop. It is not used by GCC and
should (hopefully) not be used within hand-crafted assembly.
Insert this instruction in your idle loop to reduce the cpu load on the
host.


Ignoring the MSB of the address bus
-----------------------------------
Some SoC ignores the MSB on the address bus. Thus creating a shadow memory
area. As a general rule, 0x00000000-0x7fffffff is cached, whereas
0x80000000-0xffffffff is not cached and used to access IO devices. This
behaviour can be enabled with:
  cpu_lm32_set_phys_msb_ignore(env, 1);