c79aa350ea
NPCM7XX models have been commited after the conversion from
commit 8063396bf3 ("Use OBJECT_DECLARE_SIMPLE_TYPE when possible").
Manually convert them.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230109140306.23161-11-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
113 lines
3.2 KiB
C
113 lines
3.2 KiB
C
/*
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* Nuvoton NPCM7xx SMBus Module.
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*
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* Copyright 2020 Google LLC
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*/
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#ifndef NPCM7XX_SMBUS_H
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#define NPCM7XX_SMBUS_H
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#include "exec/memory.h"
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#include "hw/i2c/i2c.h"
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#include "hw/irq.h"
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#include "hw/sysbus.h"
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/*
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* Number of addresses this module contains. Do not change this without
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* incrementing the version_id in the vmstate.
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*/
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#define NPCM7XX_SMBUS_NR_ADDRS 10
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/* Size of the FIFO buffer. */
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#define NPCM7XX_SMBUS_FIFO_SIZE 16
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typedef enum NPCM7xxSMBusStatus {
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NPCM7XX_SMBUS_STATUS_IDLE,
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NPCM7XX_SMBUS_STATUS_SENDING,
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NPCM7XX_SMBUS_STATUS_RECEIVING,
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NPCM7XX_SMBUS_STATUS_NEGACK,
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NPCM7XX_SMBUS_STATUS_STOPPING_LAST_RECEIVE,
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NPCM7XX_SMBUS_STATUS_STOPPING_NEGACK,
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} NPCM7xxSMBusStatus;
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/*
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* struct NPCM7xxSMBusState - System Management Bus device state.
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* @bus: The underlying I2C Bus.
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* @irq: GIC interrupt line to fire on events (if enabled).
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* @sda: The serial data register.
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* @st: The status register.
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* @cst: The control status register.
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* @cst2: The control status register 2.
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* @cst3: The control status register 3.
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* @ctl1: The control register 1.
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* @ctl2: The control register 2.
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* @ctl3: The control register 3.
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* @ctl4: The control register 4.
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* @ctl5: The control register 5.
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* @addr: The SMBus module's own addresses on the I2C bus.
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* @scllt: The SCL low time register.
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* @sclht: The SCL high time register.
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* @fif_ctl: The FIFO control register.
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* @fif_cts: The FIFO control status register.
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* @fair_per: The fair preriod register.
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* @txf_ctl: The transmit FIFO control register.
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* @t_out: The SMBus timeout register.
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* @txf_sts: The transmit FIFO status register.
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* @rxf_sts: The receive FIFO status register.
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* @rxf_ctl: The receive FIFO control register.
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* @rx_fifo: The FIFO buffer for receiving in FIFO mode.
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* @rx_cur: The current position of rx_fifo.
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* @status: The current status of the SMBus.
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*/
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struct NPCM7xxSMBusState {
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SysBusDevice parent;
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MemoryRegion iomem;
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I2CBus *bus;
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qemu_irq irq;
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uint8_t sda;
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uint8_t st;
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uint8_t cst;
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uint8_t cst2;
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uint8_t cst3;
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uint8_t ctl1;
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uint8_t ctl2;
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uint8_t ctl3;
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uint8_t ctl4;
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uint8_t ctl5;
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uint8_t addr[NPCM7XX_SMBUS_NR_ADDRS];
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uint8_t scllt;
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uint8_t sclht;
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uint8_t fif_ctl;
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uint8_t fif_cts;
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uint8_t fair_per;
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uint8_t txf_ctl;
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uint8_t t_out;
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uint8_t txf_sts;
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uint8_t rxf_sts;
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uint8_t rxf_ctl;
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uint8_t rx_fifo[NPCM7XX_SMBUS_FIFO_SIZE];
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uint8_t rx_cur;
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NPCM7xxSMBusStatus status;
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};
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#define TYPE_NPCM7XX_SMBUS "npcm7xx-smbus"
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OBJECT_DECLARE_SIMPLE_TYPE(NPCM7xxSMBusState, NPCM7XX_SMBUS)
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#endif /* NPCM7XX_SMBUS_H */
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