Alistair Francis 71f09a5bb4 target/riscv: Add Hypervisor CSR macros ... Add the 1.10.1 Hypervisor CSRs and remove the 1.9.1 spec versions. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>		2019-05-24 12:09:24 -07:00
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insn_trans	target/riscv: Split gen_arith_imm into functional and temp	2019-05-24 12:09:23 -07:00
cpu_bits.h	target/riscv: Add Hypervisor CSR macros	2019-05-24 12:09:24 -07:00
cpu_helper.c	target/riscv: Improve the scause logic	2019-05-24 12:09:24 -07:00
cpu_user.h	RISC-V: linux-user support for RVE ABI	2019-03-19 05:14:39 -07:00
cpu.c	target/riscv: Add a base 32 and 64 bit CPU	2019-05-24 12:09:23 -07:00
cpu.h	target/riscv: Add a base 32 and 64 bit CPU	2019-05-24 12:09:23 -07:00
csr.c	target/riscv: Allow setting mstatus virtulisation bits	2019-05-24 12:09:24 -07:00
fpu_helper.c
gdbstub.c
helper.h
insn16-32.decode	target/riscv: Split RVC32 and RVC64 insns into separate files	2019-05-24 12:09:22 -07:00
insn16-64.decode	target/riscv: Split RVC32 and RVC64 insns into separate files	2019-05-24 12:09:22 -07:00
insn16.decode	target/riscv: Split RVC32 and RVC64 insns into separate files	2019-05-24 12:09:22 -07:00
insn32-64.decode
insn32.decode	target/riscv: Name the argument sets for all of insn32 formats	2019-05-24 12:09:22 -07:00
instmap.h
Makefile.objs	target/riscv: Split RVC32 and RVC64 insns into separate files	2019-05-24 12:09:22 -07:00
op_helper.c	target/riscv: Do not allow sfence.vma from user mode	2019-05-24 12:09:19 -07:00
pmp.c
pmp.h	Clean up ill-advised or unusual header guards	2019-05-13 08:58:55 +02:00
trace-events	RISC-V: Convert trap debugging to trace events	2019-03-19 05:14:40 -07:00
translate.c	target/riscv: Split gen_arith_imm into functional and temp	2019-05-24 12:09:23 -07:00