59a71f7578
Xtensa cores may have a register (CCOUNT) that counts core clock cycles. It may also have a number of registers (CCOMPAREx); when CCOUNT value passes the value of CCOMPAREx, timer interrupt x is raised. Currently xtensa target counts a number of completed instructions and assumes that for CCOUNT one instruction takes one cycle to complete. It calls helper function to update CCOUNT register at every TB end and raise timer interrupts. This scheme works very predictably and doesn't have noticeable performance impact, but it is hard to use with multiple synchronized processors, especially with coming MTTCG. Derive CCOUNT from the virtual simulation time, QEMU_CLOCK_VIRTUAL. Use native QEMU timers for CCOMPARE timers, one timer for each register. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
122 lines
4.4 KiB
C
122 lines
4.4 KiB
C
/*
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* Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of the Open Source and Linux Lab nor the
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* names of its contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "hw/hw.h"
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#include "qemu/log.h"
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#include "qemu/timer.h"
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void check_interrupts(CPUXtensaState *env)
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{
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CPUState *cs = CPU(xtensa_env_get_cpu(env));
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int minlevel = xtensa_get_cintlevel(env);
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uint32_t int_set_enabled = env->sregs[INTSET] & env->sregs[INTENABLE];
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int level;
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for (level = env->config->nlevel; level > minlevel; --level) {
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if (env->config->level_mask[level] & int_set_enabled) {
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env->pending_irq_level = level;
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cpu_interrupt(cs, CPU_INTERRUPT_HARD);
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qemu_log_mask(CPU_LOG_INT,
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"%s level = %d, cintlevel = %d, "
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"pc = %08x, a0 = %08x, ps = %08x, "
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"intset = %08x, intenable = %08x, "
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"ccount = %08x\n",
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__func__, level, xtensa_get_cintlevel(env),
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env->pc, env->regs[0], env->sregs[PS],
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env->sregs[INTSET], env->sregs[INTENABLE],
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env->sregs[CCOUNT]);
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return;
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}
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}
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env->pending_irq_level = 0;
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cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
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}
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static void xtensa_set_irq(void *opaque, int irq, int active)
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{
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CPUXtensaState *env = opaque;
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if (irq >= env->config->ninterrupt) {
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qemu_log("%s: bad IRQ %d\n", __func__, irq);
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} else {
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uint32_t irq_bit = 1 << irq;
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if (active) {
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env->sregs[INTSET] |= irq_bit;
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} else if (env->config->interrupt[irq].inttype == INTTYPE_LEVEL) {
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env->sregs[INTSET] &= ~irq_bit;
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}
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check_interrupts(env);
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}
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}
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void xtensa_timer_irq(CPUXtensaState *env, uint32_t id, uint32_t active)
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{
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qemu_set_irq(env->irq_inputs[env->config->timerint[id]], active);
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}
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static void xtensa_ccompare_cb(void *opaque)
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{
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XtensaCcompareTimer *ccompare = opaque;
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CPUXtensaState *env = ccompare->env;
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unsigned i = ccompare - env->ccompare;
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xtensa_timer_irq(env, i, 1);
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}
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void xtensa_irq_init(CPUXtensaState *env)
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{
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env->irq_inputs = (void **)qemu_allocate_irqs(
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xtensa_set_irq, env, env->config->ninterrupt);
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if (xtensa_option_enabled(env->config, XTENSA_OPTION_TIMER_INTERRUPT)) {
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unsigned i;
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env->time_base = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
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env->ccount_base = env->sregs[CCOUNT];
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for (i = 0; i < env->config->nccompare; ++i) {
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env->ccompare[i].env = env;
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env->ccompare[i].timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
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xtensa_ccompare_cb, env->ccompare + i);
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}
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}
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}
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void *xtensa_get_extint(CPUXtensaState *env, unsigned extint)
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{
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if (extint < env->config->nextint) {
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unsigned irq = env->config->extint[extint];
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return env->irq_inputs[irq];
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} else {
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qemu_log("%s: trying to acquire invalid external interrupt %d\n",
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__func__, extint);
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return NULL;
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}
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}
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