083b266f69
The Chardev events are listed in the QEMUChrEvent enum.
By using the enum in the IOEventHandler typedef we:
- make the IOEventHandler type more explicit (this handler
process out-of-band information, while the IOReadHandler
is in-band),
- help static code analyzers.
This patch was produced with the following spatch script:
@match@
expression backend, opaque, context, set_open;
identifier fd_can_read, fd_read, fd_event, be_change;
@@
qemu_chr_fe_set_handlers(backend, fd_can_read, fd_read, fd_event,
be_change, opaque, context, set_open);
@depends on match@
identifier opaque, event;
identifier match.fd_event;
@@
static
-void fd_event(void *opaque, int event)
+void fd_event(void *opaque, QEMUChrEvent event)
{
...
}
Then the typedef was modified manually in
include/chardev/char-fe.h.
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Acked-by: Corey Minyard <cminyard@mvista.com>
Acked-by: Cornelia Huck <cohuck@redhat.com>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-Id: <20191218172009.8868-15-philmd@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
390 lines
10 KiB
C
390 lines
10 KiB
C
/*
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* Arm PrimeCell PL011 UART
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*
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* Copyright (c) 2006 CodeSourcery.
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* Written by Paul Brook
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*
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* This code is licensed under the GPL.
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*/
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/*
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* QEMU interface:
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* + sysbus MMIO region 0: device registers
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* + sysbus IRQ 0: UARTINTR (combined interrupt line)
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* + sysbus IRQ 1: UARTRXINTR (receive FIFO interrupt line)
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* + sysbus IRQ 2: UARTTXINTR (transmit FIFO interrupt line)
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* + sysbus IRQ 3: UARTRTINTR (receive timeout interrupt line)
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* + sysbus IRQ 4: UARTMSINTR (momem status interrupt line)
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* + sysbus IRQ 5: UARTEINTR (error interrupt line)
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*/
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#include "qemu/osdep.h"
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#include "hw/char/pl011.h"
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#include "hw/irq.h"
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#include "hw/sysbus.h"
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#include "migration/vmstate.h"
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#include "chardev/char-fe.h"
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#include "qemu/log.h"
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#include "qemu/module.h"
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#include "trace.h"
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#define PL011_INT_TX 0x20
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#define PL011_INT_RX 0x10
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#define PL011_FLAG_TXFE 0x80
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#define PL011_FLAG_RXFF 0x40
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#define PL011_FLAG_TXFF 0x20
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#define PL011_FLAG_RXFE 0x10
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/* Interrupt status bits in UARTRIS, UARTMIS, UARTIMSC */
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#define INT_OE (1 << 10)
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#define INT_BE (1 << 9)
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#define INT_PE (1 << 8)
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#define INT_FE (1 << 7)
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#define INT_RT (1 << 6)
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#define INT_TX (1 << 5)
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#define INT_RX (1 << 4)
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#define INT_DSR (1 << 3)
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#define INT_DCD (1 << 2)
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#define INT_CTS (1 << 1)
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#define INT_RI (1 << 0)
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#define INT_E (INT_OE | INT_BE | INT_PE | INT_FE)
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#define INT_MS (INT_RI | INT_DSR | INT_DCD | INT_CTS)
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static const unsigned char pl011_id_arm[8] =
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{ 0x11, 0x10, 0x14, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };
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static const unsigned char pl011_id_luminary[8] =
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{ 0x11, 0x00, 0x18, 0x01, 0x0d, 0xf0, 0x05, 0xb1 };
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/* Which bits in the interrupt status matter for each outbound IRQ line ? */
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static const uint32_t irqmask[] = {
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INT_E | INT_MS | INT_RT | INT_TX | INT_RX, /* combined IRQ */
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INT_RX,
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INT_TX,
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INT_RT,
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INT_MS,
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INT_E,
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};
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static void pl011_update(PL011State *s)
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{
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uint32_t flags;
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int i;
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flags = s->int_level & s->int_enabled;
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trace_pl011_irq_state(flags != 0);
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for (i = 0; i < ARRAY_SIZE(s->irq); i++) {
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qemu_set_irq(s->irq[i], (flags & irqmask[i]) != 0);
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}
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}
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static uint64_t pl011_read(void *opaque, hwaddr offset,
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unsigned size)
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{
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PL011State *s = (PL011State *)opaque;
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uint32_t c;
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uint64_t r;
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switch (offset >> 2) {
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case 0: /* UARTDR */
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s->flags &= ~PL011_FLAG_RXFF;
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c = s->read_fifo[s->read_pos];
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if (s->read_count > 0) {
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s->read_count--;
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if (++s->read_pos == 16)
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s->read_pos = 0;
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}
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if (s->read_count == 0) {
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s->flags |= PL011_FLAG_RXFE;
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}
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if (s->read_count == s->read_trigger - 1)
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s->int_level &= ~ PL011_INT_RX;
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trace_pl011_read_fifo(s->read_count);
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s->rsr = c >> 8;
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pl011_update(s);
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qemu_chr_fe_accept_input(&s->chr);
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r = c;
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break;
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case 1: /* UARTRSR */
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r = s->rsr;
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break;
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case 6: /* UARTFR */
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r = s->flags;
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break;
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case 8: /* UARTILPR */
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r = s->ilpr;
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break;
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case 9: /* UARTIBRD */
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r = s->ibrd;
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break;
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case 10: /* UARTFBRD */
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r = s->fbrd;
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break;
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case 11: /* UARTLCR_H */
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r = s->lcr;
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break;
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case 12: /* UARTCR */
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r = s->cr;
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break;
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case 13: /* UARTIFLS */
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r = s->ifl;
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break;
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case 14: /* UARTIMSC */
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r = s->int_enabled;
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break;
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case 15: /* UARTRIS */
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r = s->int_level;
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break;
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case 16: /* UARTMIS */
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r = s->int_level & s->int_enabled;
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break;
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case 18: /* UARTDMACR */
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r = s->dmacr;
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break;
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case 0x3f8 ... 0x400:
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r = s->id[(offset - 0xfe0) >> 2];
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"pl011_read: Bad offset 0x%x\n", (int)offset);
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r = 0;
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break;
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}
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trace_pl011_read(offset, r);
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return r;
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}
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static void pl011_set_read_trigger(PL011State *s)
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{
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#if 0
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/* The docs say the RX interrupt is triggered when the FIFO exceeds
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the threshold. However linux only reads the FIFO in response to an
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interrupt. Triggering the interrupt when the FIFO is non-empty seems
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to make things work. */
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if (s->lcr & 0x10)
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s->read_trigger = (s->ifl >> 1) & 0x1c;
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else
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#endif
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s->read_trigger = 1;
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}
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static void pl011_write(void *opaque, hwaddr offset,
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uint64_t value, unsigned size)
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{
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PL011State *s = (PL011State *)opaque;
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unsigned char ch;
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trace_pl011_write(offset, value);
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switch (offset >> 2) {
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case 0: /* UARTDR */
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/* ??? Check if transmitter is enabled. */
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ch = value;
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/* XXX this blocks entire thread. Rewrite to use
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* qemu_chr_fe_write and background I/O callbacks */
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qemu_chr_fe_write_all(&s->chr, &ch, 1);
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s->int_level |= PL011_INT_TX;
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pl011_update(s);
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break;
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case 1: /* UARTRSR/UARTECR */
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s->rsr = 0;
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break;
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case 6: /* UARTFR */
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/* Writes to Flag register are ignored. */
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break;
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case 8: /* UARTUARTILPR */
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s->ilpr = value;
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break;
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case 9: /* UARTIBRD */
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s->ibrd = value;
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break;
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case 10: /* UARTFBRD */
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s->fbrd = value;
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break;
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case 11: /* UARTLCR_H */
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/* Reset the FIFO state on FIFO enable or disable */
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if ((s->lcr ^ value) & 0x10) {
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s->read_count = 0;
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s->read_pos = 0;
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}
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s->lcr = value;
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pl011_set_read_trigger(s);
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break;
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case 12: /* UARTCR */
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/* ??? Need to implement the enable and loopback bits. */
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s->cr = value;
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break;
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case 13: /* UARTIFS */
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s->ifl = value;
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pl011_set_read_trigger(s);
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break;
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case 14: /* UARTIMSC */
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s->int_enabled = value;
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pl011_update(s);
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break;
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case 17: /* UARTICR */
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s->int_level &= ~value;
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pl011_update(s);
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break;
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case 18: /* UARTDMACR */
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s->dmacr = value;
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if (value & 3) {
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qemu_log_mask(LOG_UNIMP, "pl011: DMA not implemented\n");
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}
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"pl011_write: Bad offset 0x%x\n", (int)offset);
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}
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}
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static int pl011_can_receive(void *opaque)
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{
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PL011State *s = (PL011State *)opaque;
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int r;
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if (s->lcr & 0x10) {
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r = s->read_count < 16;
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} else {
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r = s->read_count < 1;
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}
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trace_pl011_can_receive(s->lcr, s->read_count, r);
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return r;
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}
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static void pl011_put_fifo(void *opaque, uint32_t value)
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{
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PL011State *s = (PL011State *)opaque;
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int slot;
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slot = s->read_pos + s->read_count;
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if (slot >= 16)
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slot -= 16;
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s->read_fifo[slot] = value;
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s->read_count++;
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s->flags &= ~PL011_FLAG_RXFE;
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trace_pl011_put_fifo(value, s->read_count);
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if (!(s->lcr & 0x10) || s->read_count == 16) {
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trace_pl011_put_fifo_full();
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s->flags |= PL011_FLAG_RXFF;
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}
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if (s->read_count == s->read_trigger) {
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s->int_level |= PL011_INT_RX;
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pl011_update(s);
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}
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}
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static void pl011_receive(void *opaque, const uint8_t *buf, int size)
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{
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pl011_put_fifo(opaque, *buf);
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}
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static void pl011_event(void *opaque, QEMUChrEvent event)
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{
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if (event == CHR_EVENT_BREAK)
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pl011_put_fifo(opaque, 0x400);
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}
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static const MemoryRegionOps pl011_ops = {
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.read = pl011_read,
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.write = pl011_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static const VMStateDescription vmstate_pl011 = {
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.name = "pl011",
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.version_id = 2,
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.minimum_version_id = 2,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(readbuff, PL011State),
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VMSTATE_UINT32(flags, PL011State),
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VMSTATE_UINT32(lcr, PL011State),
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VMSTATE_UINT32(rsr, PL011State),
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VMSTATE_UINT32(cr, PL011State),
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VMSTATE_UINT32(dmacr, PL011State),
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VMSTATE_UINT32(int_enabled, PL011State),
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VMSTATE_UINT32(int_level, PL011State),
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VMSTATE_UINT32_ARRAY(read_fifo, PL011State, 16),
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VMSTATE_UINT32(ilpr, PL011State),
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VMSTATE_UINT32(ibrd, PL011State),
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VMSTATE_UINT32(fbrd, PL011State),
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VMSTATE_UINT32(ifl, PL011State),
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VMSTATE_INT32(read_pos, PL011State),
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VMSTATE_INT32(read_count, PL011State),
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VMSTATE_INT32(read_trigger, PL011State),
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VMSTATE_END_OF_LIST()
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}
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};
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static Property pl011_properties[] = {
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DEFINE_PROP_CHR("chardev", PL011State, chr),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void pl011_init(Object *obj)
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{
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SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
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PL011State *s = PL011(obj);
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int i;
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memory_region_init_io(&s->iomem, OBJECT(s), &pl011_ops, s, "pl011", 0x1000);
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sysbus_init_mmio(sbd, &s->iomem);
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for (i = 0; i < ARRAY_SIZE(s->irq); i++) {
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sysbus_init_irq(sbd, &s->irq[i]);
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}
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s->read_trigger = 1;
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s->ifl = 0x12;
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s->cr = 0x300;
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s->flags = 0x90;
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s->id = pl011_id_arm;
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}
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static void pl011_realize(DeviceState *dev, Error **errp)
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{
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PL011State *s = PL011(dev);
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qemu_chr_fe_set_handlers(&s->chr, pl011_can_receive, pl011_receive,
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pl011_event, NULL, s, NULL, true);
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}
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static void pl011_class_init(ObjectClass *oc, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(oc);
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dc->realize = pl011_realize;
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dc->vmsd = &vmstate_pl011;
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dc->props = pl011_properties;
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}
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static const TypeInfo pl011_arm_info = {
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.name = TYPE_PL011,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(PL011State),
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.instance_init = pl011_init,
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.class_init = pl011_class_init,
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};
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static void pl011_luminary_init(Object *obj)
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{
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PL011State *s = PL011(obj);
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s->id = pl011_id_luminary;
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}
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static const TypeInfo pl011_luminary_info = {
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.name = TYPE_PL011_LUMINARY,
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.parent = TYPE_PL011,
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.instance_init = pl011_luminary_init,
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};
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static void pl011_register_types(void)
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{
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type_register_static(&pl011_arm_info);
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type_register_static(&pl011_luminary_info);
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}
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type_init(pl011_register_types)
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