92 lines
1.7 KiB
ArmAsm
92 lines
1.7 KiB
ArmAsm
#include "macros.inc"
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test_suite sr
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.macro sr_op sym, op_sym, op_byte, sr
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.if \sym
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\op_sym a4, \sr
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.else
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.byte 0x40, \sr, \op_byte
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.endif
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.endm
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.macro test_sr_op sym, mask, op, op_byte, sr
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movi a4, 0
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.if (\mask)
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set_vector kernel, 0
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sr_op \sym, \op, \op_byte, \sr
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.else
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set_vector kernel, 2f
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1:
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sr_op \sym, \op, \op_byte, \sr
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test_fail
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2:
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reset_ps
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rsr a2, exccause
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assert eqi, a2, 0
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rsr a2, epc1
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movi a3, 1b
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assert eq, a2, a3
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.endif
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.endm
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.macro test_sr_mask sr, sym, mask
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test \sr
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test_sr_op \sym, \mask & 1, rsr, 0x03, \sr
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test_sr_op \sym, \mask & 2, wsr, 0x13, \sr
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test_sr_op \sym, \mask & 4, xsr, 0x61, \sr
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test_end
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.endm
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.macro test_sr sr, conf
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test_sr_mask \sr, \conf, 7
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.endm
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test_sr acchi, 1
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test_sr acclo, 1
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test_sr /*memctl*/97, 0
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test_sr_mask /*atomctl*/99, 0, 0
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test_sr_mask /*br*/4, 0, 0
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test_sr_mask /*cacheattr*/98, 0, 0
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test_sr ccompare0, 1
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test_sr ccount, 1
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test_sr cpenable, 1
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test_sr dbreaka0, 1
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test_sr dbreakc0, 1
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test_sr_mask debugcause, 1, 1
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test_sr depc, 1
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test_sr dtlbcfg, 1
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test_sr epc1, 1
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test_sr epc2, 1
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test_sr eps2, 1
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test_sr exccause, 1
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test_sr excsave1, 1
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test_sr excsave2, 1
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test_sr excvaddr, 1
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test_sr ibreaka0, 1
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test_sr ibreakenable, 1
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test_sr icount, 1
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test_sr icountlevel, 1
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test_sr_mask /*intclear*/227, 0, 2
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test_sr_mask /*interrupt*/226, 0, 3
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test_sr intenable, 1
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test_sr itlbcfg, 1
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test_sr lbeg, 1
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test_sr lcount, 1
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test_sr lend, 1
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test_sr litbase, 1
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test_sr m0, 1
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test_sr misc0, 1
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test_sr_mask /*prefctl*/40, 0, 0
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test_sr_mask /*prid*/235, 0, 1
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test_sr ps, 1
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test_sr ptevaddr, 1
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test_sr rasid, 1
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test_sr sar, 1
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test_sr scompare1, 1
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test_sr vecbase, 1
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test_sr windowbase, 1
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test_sr windowstart, 1
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test_suite_end
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