d4a9eb1fc6
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5421 c046a42c-6fe2-441c-8c8c-71466251a162
976 lines
29 KiB
C
976 lines
29 KiB
C
/*
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* Tiny Code Generator for QEMU
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*
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* Copyright (c) 2008 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#ifndef NDEBUG
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static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
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"%r0",
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"%r1",
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"%rp",
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"%r3",
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"%r4",
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"%r5",
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"%r6",
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"%r7",
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"%r8",
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"%r9",
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"%r10",
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"%r11",
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"%r12",
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"%r13",
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"%r14",
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"%r15",
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"%r16",
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"%r17",
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"%r18",
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"%r19",
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"%r20",
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"%r21",
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"%r22",
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"%r23",
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"%r24",
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"%r25",
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"%r26",
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"%dp",
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"%ret0",
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"%ret1",
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"%sp",
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"%r31",
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};
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#endif
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static const int tcg_target_reg_alloc_order[] = {
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TCG_REG_R4,
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TCG_REG_R5,
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TCG_REG_R6,
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TCG_REG_R7,
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TCG_REG_R8,
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TCG_REG_R9,
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TCG_REG_R10,
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TCG_REG_R11,
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TCG_REG_R12,
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TCG_REG_R13,
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TCG_REG_R17,
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TCG_REG_R14,
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TCG_REG_R15,
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TCG_REG_R16,
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};
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static const int tcg_target_call_iarg_regs[4] = {
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TCG_REG_R26,
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TCG_REG_R25,
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TCG_REG_R24,
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TCG_REG_R23,
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};
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static const int tcg_target_call_oarg_regs[2] = {
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TCG_REG_RET0,
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TCG_REG_RET1,
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};
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static void patch_reloc(uint8_t *code_ptr, int type,
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tcg_target_long value, tcg_target_long addend)
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{
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switch (type) {
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case R_PARISC_PCREL17F:
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hppa_patch17f((uint32_t *)code_ptr, value, addend);
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break;
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default:
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tcg_abort();
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}
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}
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/* maximum number of register used for input function arguments */
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static inline int tcg_target_get_call_iarg_regs_count(int flags)
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{
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return 4;
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}
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/* parse target specific constraints */
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static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
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{
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const char *ct_str;
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ct_str = *pct_str;
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switch (ct_str[0]) {
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case 'r':
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ct->ct |= TCG_CT_REG;
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tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
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break;
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case 'L': /* qemu_ld/st constraint */
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ct->ct |= TCG_CT_REG;
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tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
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tcg_regset_reset_reg(ct->u.regs, TCG_REG_R26);
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tcg_regset_reset_reg(ct->u.regs, TCG_REG_R25);
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tcg_regset_reset_reg(ct->u.regs, TCG_REG_R24);
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tcg_regset_reset_reg(ct->u.regs, TCG_REG_R23);
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break;
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default:
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return -1;
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}
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ct_str++;
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*pct_str = ct_str;
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return 0;
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}
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/* test if a constant matches the constraint */
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static inline int tcg_target_const_match(tcg_target_long val,
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const TCGArgConstraint *arg_ct)
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{
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int ct;
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ct = arg_ct->ct;
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/* TODO */
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return 0;
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}
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#define INSN_OP(x) ((x) << 26)
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#define INSN_EXT3BR(x) ((x) << 13)
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#define INSN_EXT3SH(x) ((x) << 10)
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#define INSN_EXT4(x) ((x) << 6)
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#define INSN_EXT5(x) (x)
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#define INSN_EXT6(x) ((x) << 6)
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#define INSN_EXT7(x) ((x) << 6)
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#define INSN_EXT8A(x) ((x) << 6)
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#define INSN_EXT8B(x) ((x) << 5)
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#define INSN_T(x) (x)
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#define INSN_R1(x) ((x) << 16)
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#define INSN_R2(x) ((x) << 21)
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#define INSN_DEP_LEN(x) (32 - (x))
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#define INSN_SHDEP_CP(x) ((31 - (x)) << 5)
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#define INSN_SHDEP_P(x) ((x) << 5)
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#define INSN_COND(x) ((x) << 13)
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#define COND_NEVER 0
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#define COND_EQUAL 1
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#define COND_LT 2
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#define COND_LTEQ 3
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#define COND_LTU 4
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#define COND_LTUEQ 5
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#define COND_SV 6
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#define COND_OD 7
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/* Logical ADD */
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#define ARITH_ADD (INSN_OP(0x02) | INSN_EXT6(0x28))
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#define ARITH_AND (INSN_OP(0x02) | INSN_EXT6(0x08))
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#define ARITH_OR (INSN_OP(0x02) | INSN_EXT6(0x09))
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#define ARITH_XOR (INSN_OP(0x02) | INSN_EXT6(0x0a))
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#define ARITH_SUB (INSN_OP(0x02) | INSN_EXT6(0x10))
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#define SHD (INSN_OP(0x34) | INSN_EXT3SH(2))
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#define VSHD (INSN_OP(0x34) | INSN_EXT3SH(0))
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#define DEP (INSN_OP(0x35) | INSN_EXT3SH(3))
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#define ZDEP (INSN_OP(0x35) | INSN_EXT3SH(2))
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#define ZVDEP (INSN_OP(0x35) | INSN_EXT3SH(0))
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#define EXTRU (INSN_OP(0x34) | INSN_EXT3SH(6))
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#define EXTRS (INSN_OP(0x34) | INSN_EXT3SH(7))
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#define VEXTRS (INSN_OP(0x34) | INSN_EXT3SH(5))
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#define SUBI (INSN_OP(0x25))
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#define MTCTL (INSN_OP(0x00) | INSN_EXT8B(0xc2))
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#define BL (INSN_OP(0x3a) | INSN_EXT3BR(0))
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#define BLE_SR4 (INSN_OP(0x39) | (1 << 13))
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#define BV (INSN_OP(0x3a) | INSN_EXT3BR(6))
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#define BV_N (INSN_OP(0x3a) | INSN_EXT3BR(6) | 2)
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#define LDIL (INSN_OP(0x08))
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#define LDO (INSN_OP(0x0d))
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#define LDB (INSN_OP(0x10))
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#define LDH (INSN_OP(0x11))
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#define LDW (INSN_OP(0x12))
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#define LDWM (INSN_OP(0x13))
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#define STB (INSN_OP(0x18))
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#define STH (INSN_OP(0x19))
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#define STW (INSN_OP(0x1a))
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#define STWM (INSN_OP(0x1b))
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#define COMBT (INSN_OP(0x20))
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#define COMBF (INSN_OP(0x22))
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static int lowsignext(uint32_t val, int start, int length)
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{
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return (((val << 1) & ~(~0 << length)) |
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((val >> (length - 1)) & 1)) << start;
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}
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static inline void tcg_out_mov(TCGContext *s, int ret, int arg)
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{
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/* PA1.1 defines COPY as OR r,0,t */
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tcg_out32(s, ARITH_OR | INSN_T(ret) | INSN_R1(arg) | INSN_R2(TCG_REG_R0));
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/* PA2.0 defines COPY as LDO 0(r),t
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* but hppa-dis.c is unaware of this definition */
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/* tcg_out32(s, LDO | INSN_R1(ret) | INSN_R2(arg) | reassemble_14(0)); */
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}
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static inline void tcg_out_movi(TCGContext *s, TCGType type,
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int ret, tcg_target_long arg)
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{
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if (arg == (arg & 0x1fff)) {
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tcg_out32(s, LDO | INSN_R1(ret) | INSN_R2(TCG_REG_R0) |
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reassemble_14(arg));
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} else {
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tcg_out32(s, LDIL | INSN_R2(ret) |
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reassemble_21(lrsel((uint32_t)arg, 0)));
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if (arg & 0x7ff)
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tcg_out32(s, LDO | INSN_R1(ret) | INSN_R2(ret) |
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reassemble_14(rrsel((uint32_t)arg, 0)));
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}
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}
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static inline void tcg_out_ld_raw(TCGContext *s, int ret,
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tcg_target_long arg)
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{
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tcg_out32(s, LDIL | INSN_R2(ret) |
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reassemble_21(lrsel((uint32_t)arg, 0)));
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tcg_out32(s, LDW | INSN_R1(ret) | INSN_R2(ret) |
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reassemble_14(rrsel((uint32_t)arg, 0)));
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}
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static inline void tcg_out_ld_ptr(TCGContext *s, int ret,
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tcg_target_long arg)
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{
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tcg_out_ld_raw(s, ret, arg);
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}
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static inline void tcg_out_ldst(TCGContext *s, int ret, int addr, int offset,
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int op)
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{
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if (offset == (offset & 0xfff))
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tcg_out32(s, op | INSN_R1(ret) | INSN_R2(addr) |
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reassemble_14(offset));
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else {
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fprintf(stderr, "unimplemented %s with offset %d\n", __func__, offset);
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tcg_abort();
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}
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}
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static inline void tcg_out_ld(TCGContext *s, TCGType type, int ret,
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int arg1, tcg_target_long arg2)
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{
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fprintf(stderr, "unimplemented %s\n", __func__);
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tcg_abort();
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}
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static inline void tcg_out_st(TCGContext *s, TCGType type, int ret,
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int arg1, tcg_target_long arg2)
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{
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fprintf(stderr, "unimplemented %s\n", __func__);
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tcg_abort();
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}
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static inline void tcg_out_arith(TCGContext *s, int t, int r1, int r2, int op)
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{
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tcg_out32(s, op | INSN_T(t) | INSN_R1(r1) | INSN_R2(r2));
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}
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static inline void tcg_out_arithi(TCGContext *s, int t, int r1,
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tcg_target_long val, int op)
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{
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tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R20, val);
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tcg_out_arith(s, t, r1, TCG_REG_R20, op);
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}
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static inline void tcg_out_addi(TCGContext *s, int reg, tcg_target_long val)
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{
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tcg_out_arithi(s, reg, reg, val, ARITH_ADD);
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}
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static inline void tcg_out_nop(TCGContext *s)
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{
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tcg_out32(s, ARITH_OR | INSN_T(TCG_REG_R0) | INSN_R1(TCG_REG_R0) |
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INSN_R2(TCG_REG_R0));
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}
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static inline void tcg_out_ext8s(TCGContext *s, int ret, int arg) {
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tcg_out32(s, EXTRS | INSN_R1(ret) | INSN_R2(arg) |
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INSN_SHDEP_P(31) | INSN_DEP_LEN(8));
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}
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static inline void tcg_out_ext16s(TCGContext *s, int ret, int arg) {
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tcg_out32(s, EXTRS | INSN_R1(ret) | INSN_R2(arg) |
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INSN_SHDEP_P(31) | INSN_DEP_LEN(16));
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}
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static inline void tcg_out_bswap16(TCGContext *s, int ret, int arg) {
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if(ret != arg)
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tcg_out_mov(s, ret, arg);
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tcg_out32(s, DEP | INSN_R2(ret) | INSN_R1(ret) |
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INSN_SHDEP_CP(15) | INSN_DEP_LEN(8));
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tcg_out32(s, SHD | INSN_T(ret) | INSN_R1(TCG_REG_R0) |
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INSN_R2(ret) | INSN_SHDEP_CP(8));
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}
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static inline void tcg_out_bswap32(TCGContext *s, int ret, int arg, int temp) {
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tcg_out32(s, SHD | INSN_T(temp) | INSN_R1(arg) |
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INSN_R2(arg) | INSN_SHDEP_CP(16));
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tcg_out32(s, DEP | INSN_R2(temp) | INSN_R1(temp) |
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INSN_SHDEP_CP(15) | INSN_DEP_LEN(8));
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tcg_out32(s, SHD | INSN_T(ret) | INSN_R1(arg) |
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INSN_R2(temp) | INSN_SHDEP_CP(8));
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}
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static inline void tcg_out_call(TCGContext *s, void *func)
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{
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uint32_t val = (uint32_t)__canonicalize_funcptr_for_compare(func);
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tcg_out32(s, LDIL | INSN_R2(TCG_REG_R20) |
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reassemble_21(lrsel(val, 0)));
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tcg_out32(s, BLE_SR4 | INSN_R2(TCG_REG_R20) |
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reassemble_17(rrsel(val, 0) >> 2));
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tcg_out_mov(s, TCG_REG_RP, TCG_REG_R31);
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}
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#if defined(CONFIG_SOFTMMU)
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#include "../../softmmu_defs.h"
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static void *qemu_ld_helpers[4] = {
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__ldb_mmu,
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__ldw_mmu,
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__ldl_mmu,
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__ldq_mmu,
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};
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static void *qemu_st_helpers[4] = {
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__stb_mmu,
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__stw_mmu,
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__stl_mmu,
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__stq_mmu,
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};
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#endif
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static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
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{
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int addr_reg, data_reg, data_reg2, r0, r1, mem_index, s_bits, bswap;
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#if defined(CONFIG_SOFTMMU)
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uint32_t *label1_ptr, *label2_ptr;
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#endif
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#if TARGET_LONG_BITS == 64
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#if defined(CONFIG_SOFTMMU)
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uint32_t *label3_ptr;
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#endif
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int addr_reg2;
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#endif
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data_reg = *args++;
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if (opc == 3)
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data_reg2 = *args++;
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else
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data_reg2 = 0; /* surpress warning */
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addr_reg = *args++;
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#if TARGET_LONG_BITS == 64
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addr_reg2 = *args++;
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#endif
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mem_index = *args;
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s_bits = opc & 3;
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r0 = TCG_REG_R26;
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r1 = TCG_REG_R25;
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#if defined(CONFIG_SOFTMMU)
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tcg_out_mov(s, r1, addr_reg);
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tcg_out_mov(s, r0, addr_reg);
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tcg_out32(s, SHD | INSN_T(r1) | INSN_R1(TCG_REG_R0) | INSN_R2(r1) |
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INSN_SHDEP_CP(TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS));
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tcg_out_arithi(s, r0, r0, TARGET_PAGE_MASK | ((1 << s_bits) - 1),
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ARITH_AND);
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tcg_out_arithi(s, r1, r1, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS,
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ARITH_AND);
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tcg_out_arith(s, r1, r1, TCG_AREG0, ARITH_ADD);
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tcg_out_arithi(s, r1, r1,
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offsetof(CPUState, tlb_table[mem_index][0].addr_read),
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ARITH_ADD);
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tcg_out_ldst(s, TCG_REG_R20, r1, 0, LDW);
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#if TARGET_LONG_BITS == 32
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/* if equal, jump to label1 */
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label1_ptr = (uint32_t *)s->code_ptr;
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tcg_out32(s, COMBT | INSN_R1(TCG_REG_R20) | INSN_R2(r0) |
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INSN_COND(COND_EQUAL));
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tcg_out_mov(s, r0, addr_reg); /* delay slot */
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#else
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/* if not equal, jump to label3 */
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label3_ptr = (uint32_t *)s->code_ptr;
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tcg_out32(s, COMBF | INSN_R1(TCG_REG_R20) | INSN_R2(r0) |
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INSN_COND(COND_EQUAL));
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tcg_out_mov(s, r0, addr_reg); /* delay slot */
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tcg_out_ldst(s, TCG_REG_R20, r1, 4, LDW);
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/* if equal, jump to label1 */
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label1_ptr = (uint32_t *)s->code_ptr;
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tcg_out32(s, COMBT | INSN_R1(TCG_REG_R20) | INSN_R2(addr_reg2) |
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INSN_COND(COND_EQUAL));
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tcg_out_nop(s); /* delay slot */
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|
/* label3: */
|
|
*label3_ptr |= reassemble_12((uint32_t *)s->code_ptr - label3_ptr - 2);
|
|
#endif
|
|
|
|
#if TARGET_LONG_BITS == 32
|
|
tcg_out_mov(s, TCG_REG_R26, addr_reg);
|
|
tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_R25, mem_index);
|
|
#else
|
|
tcg_out_mov(s, TCG_REG_R26, addr_reg);
|
|
tcg_out_mov(s, TCG_REG_R25, addr_reg2);
|
|
tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_R24, mem_index);
|
|
#endif
|
|
|
|
tcg_out_call(s, qemu_ld_helpers[s_bits]);
|
|
|
|
switch(opc) {
|
|
case 0 | 4:
|
|
tcg_out_ext8s(s, data_reg, TCG_REG_RET0);
|
|
break;
|
|
case 1 | 4:
|
|
tcg_out_ext16s(s, data_reg, TCG_REG_RET0);
|
|
break;
|
|
case 0:
|
|
case 1:
|
|
case 2:
|
|
default:
|
|
tcg_out_mov(s, data_reg, TCG_REG_RET0);
|
|
break;
|
|
case 3:
|
|
tcg_abort();
|
|
tcg_out_mov(s, data_reg, TCG_REG_RET0);
|
|
tcg_out_mov(s, data_reg2, TCG_REG_RET1);
|
|
break;
|
|
}
|
|
|
|
/* jump to label2 */
|
|
label2_ptr = (uint32_t *)s->code_ptr;
|
|
tcg_out32(s, BL | INSN_R2(TCG_REG_R0) | 2);
|
|
|
|
/* label1: */
|
|
*label1_ptr |= reassemble_12((uint32_t *)s->code_ptr - label1_ptr - 2);
|
|
|
|
tcg_out_arithi(s, TCG_REG_R20, r1,
|
|
offsetof(CPUTLBEntry, addend) - offsetof(CPUTLBEntry, addr_read),
|
|
ARITH_ADD);
|
|
tcg_out_ldst(s, TCG_REG_R20, TCG_REG_R20, 0, LDW);
|
|
tcg_out_arith(s, r0, r0, TCG_REG_R20, ARITH_ADD);
|
|
#else
|
|
r0 = addr_reg;
|
|
#endif
|
|
|
|
#ifdef TARGET_WORDS_BIGENDIAN
|
|
bswap = 0;
|
|
#else
|
|
bswap = 1;
|
|
#endif
|
|
switch (opc) {
|
|
case 0:
|
|
tcg_out_ldst(s, data_reg, r0, 0, LDB);
|
|
break;
|
|
case 0 | 4:
|
|
tcg_out_ldst(s, data_reg, r0, 0, LDB);
|
|
tcg_out_ext8s(s, data_reg, data_reg);
|
|
break;
|
|
case 1:
|
|
tcg_out_ldst(s, data_reg, r0, 0, LDH);
|
|
if (bswap)
|
|
tcg_out_bswap16(s, data_reg, data_reg);
|
|
break;
|
|
case 1 | 4:
|
|
tcg_out_ldst(s, data_reg, r0, 0, LDH);
|
|
if (bswap)
|
|
tcg_out_bswap16(s, data_reg, data_reg);
|
|
tcg_out_ext16s(s, data_reg, data_reg);
|
|
break;
|
|
case 2:
|
|
tcg_out_ldst(s, data_reg, r0, 0, LDW);
|
|
if (bswap)
|
|
tcg_out_bswap32(s, data_reg, data_reg, TCG_REG_R20);
|
|
break;
|
|
case 3:
|
|
tcg_abort();
|
|
if (!bswap) {
|
|
tcg_out_ldst(s, data_reg, r0, 0, LDW);
|
|
tcg_out_ldst(s, data_reg2, r0, 4, LDW);
|
|
} else {
|
|
tcg_out_ldst(s, data_reg, r0, 4, LDW);
|
|
tcg_out_bswap32(s, data_reg, data_reg, TCG_REG_R20);
|
|
tcg_out_ldst(s, data_reg2, r0, 0, LDW);
|
|
tcg_out_bswap32(s, data_reg2, data_reg2, TCG_REG_R20);
|
|
}
|
|
break;
|
|
default:
|
|
tcg_abort();
|
|
}
|
|
|
|
#if defined(CONFIG_SOFTMMU)
|
|
/* label2: */
|
|
*label2_ptr |= reassemble_17((uint32_t *)s->code_ptr - label2_ptr - 2);
|
|
#endif
|
|
}
|
|
|
|
static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
|
|
{
|
|
int addr_reg, data_reg, data_reg2, r0, r1, mem_index, s_bits, bswap;
|
|
#if defined(CONFIG_SOFTMMU)
|
|
uint32_t *label1_ptr, *label2_ptr;
|
|
#endif
|
|
#if TARGET_LONG_BITS == 64
|
|
#if defined(CONFIG_SOFTMMU)
|
|
uint32_t *label3_ptr;
|
|
#endif
|
|
int addr_reg2;
|
|
#endif
|
|
|
|
data_reg = *args++;
|
|
if (opc == 3)
|
|
data_reg2 = *args++;
|
|
else
|
|
data_reg2 = 0; /* surpress warning */
|
|
addr_reg = *args++;
|
|
#if TARGET_LONG_BITS == 64
|
|
addr_reg2 = *args++;
|
|
#endif
|
|
mem_index = *args;
|
|
|
|
s_bits = opc;
|
|
|
|
r0 = TCG_REG_R26;
|
|
r1 = TCG_REG_R25;
|
|
|
|
#if defined(CONFIG_SOFTMMU)
|
|
tcg_out_mov(s, r1, addr_reg);
|
|
|
|
tcg_out_mov(s, r0, addr_reg);
|
|
|
|
tcg_out32(s, SHD | INSN_T(r1) | INSN_R1(TCG_REG_R0) | INSN_R2(r1) |
|
|
INSN_SHDEP_CP(TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS));
|
|
|
|
tcg_out_arithi(s, r0, r0, TARGET_PAGE_MASK | ((1 << s_bits) - 1),
|
|
ARITH_AND);
|
|
|
|
tcg_out_arithi(s, r1, r1, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS,
|
|
ARITH_AND);
|
|
|
|
tcg_out_arith(s, r1, r1, TCG_AREG0, ARITH_ADD);
|
|
tcg_out_arithi(s, r1, r1,
|
|
offsetof(CPUState, tlb_table[mem_index][0].addr_write),
|
|
ARITH_ADD);
|
|
|
|
tcg_out_ldst(s, TCG_REG_R20, r1, 0, LDW);
|
|
|
|
#if TARGET_LONG_BITS == 32
|
|
/* if equal, jump to label1 */
|
|
label1_ptr = (uint32_t *)s->code_ptr;
|
|
tcg_out32(s, COMBT | INSN_R1(TCG_REG_R20) | INSN_R2(r0) |
|
|
INSN_COND(COND_EQUAL));
|
|
tcg_out_mov(s, r0, addr_reg); /* delay slot */
|
|
#else
|
|
/* if not equal, jump to label3 */
|
|
label3_ptr = (uint32_t *)s->code_ptr;
|
|
tcg_out32(s, COMBF | INSN_R1(TCG_REG_R20) | INSN_R2(r0) |
|
|
INSN_COND(COND_EQUAL));
|
|
tcg_out_mov(s, r0, addr_reg); /* delay slot */
|
|
|
|
tcg_out_ldst(s, TCG_REG_R20, r1, 4, LDW);
|
|
|
|
/* if equal, jump to label1 */
|
|
label1_ptr = (uint32_t *)s->code_ptr;
|
|
tcg_out32(s, COMBT | INSN_R1(TCG_REG_R20) | INSN_R2(addr_reg2) |
|
|
INSN_COND(COND_EQUAL));
|
|
tcg_out_nop(s); /* delay slot */
|
|
|
|
/* label3: */
|
|
*label3_ptr |= reassemble_12((uint32_t *)s->code_ptr - label3_ptr - 2);
|
|
#endif
|
|
|
|
tcg_out_mov(s, TCG_REG_R26, addr_reg);
|
|
#if TARGET_LONG_BITS == 64
|
|
tcg_out_mov(s, TCG_REG_R25, addr_reg2);
|
|
if (opc == 3) {
|
|
tcg_abort();
|
|
tcg_out_mov(s, TCG_REG_R24, data_reg);
|
|
tcg_out_mov(s, TCG_REG_R23, data_reg2);
|
|
/* TODO: push mem_index */
|
|
tcg_abort();
|
|
} else {
|
|
switch(opc) {
|
|
case 0:
|
|
tcg_out32(s, EXTRU | INSN_R1(TCG_REG_R24) | INSN_R2(data_reg) |
|
|
INSN_SHDEP_P(31) | INSN_DEP_LEN(8));
|
|
break;
|
|
case 1:
|
|
tcg_out32(s, EXTRU | INSN_R1(TCG_REG_R24) | INSN_R2(data_reg) |
|
|
INSN_SHDEP_P(31) | INSN_DEP_LEN(16));
|
|
break;
|
|
case 2:
|
|
tcg_out_mov(s, TCG_REG_R24, data_reg);
|
|
break;
|
|
}
|
|
tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_R23, mem_index);
|
|
}
|
|
#else
|
|
if (opc == 3) {
|
|
tcg_abort();
|
|
tcg_out_mov(s, TCG_REG_R25, data_reg);
|
|
tcg_out_mov(s, TCG_REG_R24, data_reg2);
|
|
tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_R23, mem_index);
|
|
} else {
|
|
switch(opc) {
|
|
case 0:
|
|
tcg_out32(s, EXTRU | INSN_R1(TCG_REG_R25) | INSN_R2(data_reg) |
|
|
INSN_SHDEP_P(31) | INSN_DEP_LEN(8));
|
|
break;
|
|
case 1:
|
|
tcg_out32(s, EXTRU | INSN_R1(TCG_REG_R25) | INSN_R2(data_reg) |
|
|
INSN_SHDEP_P(31) | INSN_DEP_LEN(16));
|
|
break;
|
|
case 2:
|
|
tcg_out_mov(s, TCG_REG_R25, data_reg);
|
|
break;
|
|
}
|
|
tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_R24, mem_index);
|
|
}
|
|
#endif
|
|
tcg_out_call(s, qemu_st_helpers[s_bits]);
|
|
|
|
/* jump to label2 */
|
|
label2_ptr = (uint32_t *)s->code_ptr;
|
|
tcg_out32(s, BL | INSN_R2(TCG_REG_R0) | 2);
|
|
|
|
/* label1: */
|
|
*label1_ptr |= reassemble_12((uint32_t *)s->code_ptr - label1_ptr - 2);
|
|
|
|
tcg_out_arithi(s, TCG_REG_R20, r1,
|
|
offsetof(CPUTLBEntry, addend) - offsetof(CPUTLBEntry, addr_write),
|
|
ARITH_ADD);
|
|
tcg_out_ldst(s, TCG_REG_R20, TCG_REG_R20, 0, LDW);
|
|
tcg_out_arith(s, r0, r0, TCG_REG_R20, ARITH_ADD);
|
|
#else
|
|
r0 = addr_reg;
|
|
#endif
|
|
|
|
#ifdef TARGET_WORDS_BIGENDIAN
|
|
bswap = 0;
|
|
#else
|
|
bswap = 1;
|
|
#endif
|
|
switch (opc) {
|
|
case 0:
|
|
tcg_out_ldst(s, data_reg, r0, 0, STB);
|
|
break;
|
|
case 1:
|
|
if (bswap) {
|
|
tcg_out_bswap16(s, TCG_REG_R20, data_reg);
|
|
data_reg = TCG_REG_R20;
|
|
}
|
|
tcg_out_ldst(s, data_reg, r0, 0, STH);
|
|
break;
|
|
case 2:
|
|
if (bswap) {
|
|
tcg_out_bswap32(s, TCG_REG_R20, data_reg, TCG_REG_R20);
|
|
data_reg = TCG_REG_R20;
|
|
}
|
|
tcg_out_ldst(s, data_reg, r0, 0, STW);
|
|
break;
|
|
case 3:
|
|
tcg_abort();
|
|
if (!bswap) {
|
|
tcg_out_ldst(s, data_reg, r0, 0, STW);
|
|
tcg_out_ldst(s, data_reg2, r0, 4, STW);
|
|
} else {
|
|
tcg_out_bswap32(s, TCG_REG_R20, data_reg, TCG_REG_R20);
|
|
tcg_out_ldst(s, TCG_REG_R20, r0, 4, STW);
|
|
tcg_out_bswap32(s, TCG_REG_R20, data_reg2, TCG_REG_R20);
|
|
tcg_out_ldst(s, TCG_REG_R20, r0, 0, STW);
|
|
}
|
|
break;
|
|
default:
|
|
tcg_abort();
|
|
}
|
|
|
|
#if defined(CONFIG_SOFTMMU)
|
|
/* label2: */
|
|
*label2_ptr |= reassemble_17((uint32_t *)s->code_ptr - label2_ptr - 2);
|
|
#endif
|
|
}
|
|
|
|
static inline void tcg_out_op(TCGContext *s, int opc, const TCGArg *args,
|
|
const int *const_args)
|
|
{
|
|
int c;
|
|
|
|
switch (opc) {
|
|
case INDEX_op_exit_tb:
|
|
tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_RET0, args[0]);
|
|
tcg_out32(s, BV_N | INSN_R2(TCG_REG_R18));
|
|
break;
|
|
case INDEX_op_goto_tb:
|
|
if (s->tb_jmp_offset) {
|
|
/* direct jump method */
|
|
fprintf(stderr, "goto_tb direct\n");
|
|
tcg_abort();
|
|
tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R20, args[0]);
|
|
tcg_out32(s, BV_N | INSN_R2(TCG_REG_R20));
|
|
s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
|
|
} else {
|
|
/* indirect jump method */
|
|
tcg_out_ld_ptr(s, TCG_REG_R20,
|
|
(tcg_target_long)(s->tb_next + args[0]));
|
|
tcg_out32(s, BV_N | INSN_R2(TCG_REG_R20));
|
|
}
|
|
s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf;
|
|
break;
|
|
case INDEX_op_call:
|
|
tcg_out32(s, BLE_SR4 | INSN_R2(args[0]));
|
|
tcg_out_mov(s, TCG_REG_RP, TCG_REG_R31);
|
|
break;
|
|
case INDEX_op_jmp:
|
|
fprintf(stderr, "unimplemented jmp\n");
|
|
tcg_abort();
|
|
break;
|
|
case INDEX_op_br:
|
|
fprintf(stderr, "unimplemented br\n");
|
|
tcg_abort();
|
|
break;
|
|
case INDEX_op_movi_i32:
|
|
tcg_out_movi(s, TCG_TYPE_I32, args[0], (uint32_t)args[1]);
|
|
break;
|
|
|
|
case INDEX_op_ld8u_i32:
|
|
tcg_out_ldst(s, args[0], args[1], args[2], LDB);
|
|
break;
|
|
case INDEX_op_ld8s_i32:
|
|
tcg_out_ldst(s, args[0], args[1], args[2], LDB);
|
|
tcg_out_ext8s(s, args[0], args[0]);
|
|
break;
|
|
case INDEX_op_ld16u_i32:
|
|
tcg_out_ldst(s, args[0], args[1], args[2], LDH);
|
|
break;
|
|
case INDEX_op_ld16s_i32:
|
|
tcg_out_ldst(s, args[0], args[1], args[2], LDH);
|
|
tcg_out_ext16s(s, args[0], args[0]);
|
|
break;
|
|
case INDEX_op_ld_i32:
|
|
tcg_out_ldst(s, args[0], args[1], args[2], LDW);
|
|
break;
|
|
|
|
case INDEX_op_st8_i32:
|
|
tcg_out_ldst(s, args[0], args[1], args[2], STB);
|
|
break;
|
|
case INDEX_op_st16_i32:
|
|
tcg_out_ldst(s, args[0], args[1], args[2], STH);
|
|
break;
|
|
case INDEX_op_st_i32:
|
|
tcg_out_ldst(s, args[0], args[1], args[2], STW);
|
|
break;
|
|
|
|
case INDEX_op_sub_i32:
|
|
c = ARITH_SUB;
|
|
goto gen_arith;
|
|
case INDEX_op_and_i32:
|
|
c = ARITH_AND;
|
|
goto gen_arith;
|
|
case INDEX_op_or_i32:
|
|
c = ARITH_OR;
|
|
goto gen_arith;
|
|
case INDEX_op_xor_i32:
|
|
c = ARITH_XOR;
|
|
goto gen_arith;
|
|
case INDEX_op_add_i32:
|
|
c = ARITH_ADD;
|
|
goto gen_arith;
|
|
|
|
case INDEX_op_shl_i32:
|
|
tcg_out32(s, SUBI | INSN_R1(TCG_REG_R20) | INSN_R2(args[2]) |
|
|
lowsignext(0x1f, 0, 11));
|
|
tcg_out32(s, MTCTL | INSN_R2(11) | INSN_R1(TCG_REG_R20));
|
|
tcg_out32(s, ZVDEP | INSN_R2(args[0]) | INSN_R1(args[1]) |
|
|
INSN_DEP_LEN(32));
|
|
break;
|
|
case INDEX_op_shr_i32:
|
|
tcg_out32(s, MTCTL | INSN_R2(11) | INSN_R1(args[2]));
|
|
tcg_out32(s, VSHD | INSN_T(args[0]) | INSN_R1(TCG_REG_R0) |
|
|
INSN_R2(args[1]));
|
|
break;
|
|
case INDEX_op_sar_i32:
|
|
tcg_out32(s, SUBI | INSN_R1(TCG_REG_R20) | INSN_R2(args[2]) |
|
|
lowsignext(0x1f, 0, 11));
|
|
tcg_out32(s, MTCTL | INSN_R2(11) | INSN_R1(TCG_REG_R20));
|
|
tcg_out32(s, VEXTRS | INSN_R1(args[0]) | INSN_R2(args[1]) |
|
|
INSN_DEP_LEN(32));
|
|
break;
|
|
|
|
case INDEX_op_mul_i32:
|
|
fprintf(stderr, "unimplemented mul\n");
|
|
tcg_abort();
|
|
break;
|
|
case INDEX_op_mulu2_i32:
|
|
fprintf(stderr, "unimplemented mulu2\n");
|
|
tcg_abort();
|
|
break;
|
|
case INDEX_op_div2_i32:
|
|
fprintf(stderr, "unimplemented div2\n");
|
|
tcg_abort();
|
|
break;
|
|
case INDEX_op_divu2_i32:
|
|
fprintf(stderr, "unimplemented divu2\n");
|
|
tcg_abort();
|
|
break;
|
|
|
|
case INDEX_op_brcond_i32:
|
|
fprintf(stderr, "unimplemented brcond\n");
|
|
tcg_abort();
|
|
break;
|
|
|
|
case INDEX_op_qemu_ld8u:
|
|
tcg_out_qemu_ld(s, args, 0);
|
|
break;
|
|
case INDEX_op_qemu_ld8s:
|
|
tcg_out_qemu_ld(s, args, 0 | 4);
|
|
break;
|
|
case INDEX_op_qemu_ld16u:
|
|
tcg_out_qemu_ld(s, args, 1);
|
|
break;
|
|
case INDEX_op_qemu_ld16s:
|
|
tcg_out_qemu_ld(s, args, 1 | 4);
|
|
break;
|
|
case INDEX_op_qemu_ld32u:
|
|
tcg_out_qemu_ld(s, args, 2);
|
|
break;
|
|
|
|
case INDEX_op_qemu_st8:
|
|
tcg_out_qemu_st(s, args, 0);
|
|
break;
|
|
case INDEX_op_qemu_st16:
|
|
tcg_out_qemu_st(s, args, 1);
|
|
break;
|
|
case INDEX_op_qemu_st32:
|
|
tcg_out_qemu_st(s, args, 2);
|
|
break;
|
|
|
|
default:
|
|
fprintf(stderr, "unknown opcode 0x%x\n", opc);
|
|
tcg_abort();
|
|
}
|
|
return;
|
|
|
|
gen_arith:
|
|
tcg_out_arith(s, args[0], args[1], args[2], c);
|
|
}
|
|
|
|
static const TCGTargetOpDef hppa_op_defs[] = {
|
|
{ INDEX_op_exit_tb, { } },
|
|
{ INDEX_op_goto_tb, { } },
|
|
|
|
{ INDEX_op_call, { "r" } },
|
|
{ INDEX_op_jmp, { "r" } },
|
|
{ INDEX_op_br, { } },
|
|
|
|
{ INDEX_op_mov_i32, { "r", "r" } },
|
|
{ INDEX_op_movi_i32, { "r" } },
|
|
{ INDEX_op_ld8u_i32, { "r", "r" } },
|
|
{ INDEX_op_ld8s_i32, { "r", "r" } },
|
|
{ INDEX_op_ld16u_i32, { "r", "r" } },
|
|
{ INDEX_op_ld16s_i32, { "r", "r" } },
|
|
{ INDEX_op_ld_i32, { "r", "r" } },
|
|
{ INDEX_op_st8_i32, { "r", "r" } },
|
|
{ INDEX_op_st16_i32, { "r", "r" } },
|
|
{ INDEX_op_st_i32, { "r", "r" } },
|
|
|
|
{ INDEX_op_add_i32, { "r", "r", "r" } },
|
|
{ INDEX_op_sub_i32, { "r", "r", "r" } },
|
|
{ INDEX_op_and_i32, { "r", "r", "r" } },
|
|
{ INDEX_op_or_i32, { "r", "r", "r" } },
|
|
{ INDEX_op_xor_i32, { "r", "r", "r" } },
|
|
|
|
{ INDEX_op_shl_i32, { "r", "r", "r" } },
|
|
{ INDEX_op_shr_i32, { "r", "r", "r" } },
|
|
{ INDEX_op_sar_i32, { "r", "r", "r" } },
|
|
|
|
{ INDEX_op_brcond_i32, { "r", "r" } },
|
|
|
|
#if TARGET_LONG_BITS == 32
|
|
{ INDEX_op_qemu_ld8u, { "r", "L" } },
|
|
{ INDEX_op_qemu_ld8s, { "r", "L" } },
|
|
{ INDEX_op_qemu_ld16u, { "r", "L" } },
|
|
{ INDEX_op_qemu_ld16s, { "r", "L" } },
|
|
{ INDEX_op_qemu_ld32u, { "r", "L" } },
|
|
{ INDEX_op_qemu_ld64, { "r", "r", "L" } },
|
|
|
|
{ INDEX_op_qemu_st8, { "L", "L" } },
|
|
{ INDEX_op_qemu_st16, { "L", "L" } },
|
|
{ INDEX_op_qemu_st32, { "L", "L" } },
|
|
{ INDEX_op_qemu_st64, { "L", "L", "L" } },
|
|
#else
|
|
{ INDEX_op_qemu_ld8u, { "r", "L", "L" } },
|
|
{ INDEX_op_qemu_ld8s, { "r", "L", "L" } },
|
|
{ INDEX_op_qemu_ld16u, { "r", "L", "L" } },
|
|
{ INDEX_op_qemu_ld16s, { "r", "L", "L" } },
|
|
{ INDEX_op_qemu_ld32u, { "r", "L", "L" } },
|
|
{ INDEX_op_qemu_ld32s, { "r", "L", "L" } },
|
|
{ INDEX_op_qemu_ld64, { "r", "r", "L", "L" } },
|
|
|
|
{ INDEX_op_qemu_st8, { "L", "L", "L" } },
|
|
{ INDEX_op_qemu_st16, { "L", "L", "L" } },
|
|
{ INDEX_op_qemu_st32, { "L", "L", "L" } },
|
|
{ INDEX_op_qemu_st64, { "L", "L", "L", "L" } },
|
|
#endif
|
|
{ -1 },
|
|
};
|
|
|
|
void tcg_target_init(TCGContext *s)
|
|
{
|
|
tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffffffff);
|
|
tcg_regset_set32(tcg_target_call_clobber_regs, 0,
|
|
(1 << TCG_REG_R20) |
|
|
(1 << TCG_REG_R21) |
|
|
(1 << TCG_REG_R22) |
|
|
(1 << TCG_REG_R23) |
|
|
(1 << TCG_REG_R24) |
|
|
(1 << TCG_REG_R25) |
|
|
(1 << TCG_REG_R26));
|
|
|
|
tcg_regset_clear(s->reserved_regs);
|
|
tcg_regset_set_reg(s->reserved_regs, TCG_REG_R0); /* hardwired to zero */
|
|
tcg_regset_set_reg(s->reserved_regs, TCG_REG_R1); /* addil target */
|
|
tcg_regset_set_reg(s->reserved_regs, TCG_REG_RP); /* link register */
|
|
tcg_regset_set_reg(s->reserved_regs, TCG_REG_R3); /* frame pointer */
|
|
tcg_regset_set_reg(s->reserved_regs, TCG_REG_R18); /* return pointer */
|
|
tcg_regset_set_reg(s->reserved_regs, TCG_REG_R19); /* clobbered w/o pic */
|
|
tcg_regset_set_reg(s->reserved_regs, TCG_REG_R20); /* reserved */
|
|
tcg_regset_set_reg(s->reserved_regs, TCG_REG_DP); /* data pointer */
|
|
tcg_regset_set_reg(s->reserved_regs, TCG_REG_SP); /* stack pointer */
|
|
tcg_regset_set_reg(s->reserved_regs, TCG_REG_R31); /* ble link reg */
|
|
|
|
tcg_add_target_add_op_defs(hppa_op_defs);
|
|
}
|