qemu-e2k/target/riscv
Claudio Fontana 740b175973 cpu-timers, icount: new modules
refactoring of cpus.c continues with cpu timer state extraction.

cpu-timers: responsible for the softmmu cpu timers state,
            including cpu clocks and ticks.

icount: counts the TCG instructions executed. As such it is specific to
the TCG accelerator. Therefore, it is built only under CONFIG_TCG.

One complication is due to qtest, which uses an icount field to warp time
as part of qtest (qtest_clock_warp).

In order to solve this problem, provide a separate counter for qtest.

This requires fixing assumptions scattered in the code that
qtest_enabled() implies icount_enabled(), checking each specific case.

Signed-off-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
[remove redundant initialization with qemu_spice_init]
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
[fix lingering calls to icount_get]
Signed-off-by: Claudio Fontana <cfontana@suse.de>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-10-05 16:41:22 +02:00
..
insn_trans target/riscv: Support the Virtual Instruction fault 2020-08-25 09:11:36 -07:00
cpu_bits.h target/riscv: Support the Virtual Instruction fault 2020-08-25 09:11:36 -07:00
cpu_helper.c qemu/atomic.h: rename atomic_ to qatomic_ 2020-09-23 16:07:44 +01:00
cpu_user.h
cpu-param.h
cpu.c target/riscv: Set instance_align on RISCVCPU TypeInfo 2020-09-18 13:59:51 -04:00
cpu.h qom: Remove module_obj_name parameter from OBJECT_DECLARE* macros 2020-09-18 14:12:32 -04:00
csr.c cpu-timers, icount: new modules 2020-10-05 16:41:22 +02:00
fpu_helper.c target/riscv: Check nanboxed inputs to fp helpers 2020-08-21 22:37:55 -07:00
gdbstub.c
helper.h target/riscv: Support the Virtual Instruction fault 2020-08-25 09:11:36 -07:00
insn16-32.decode
insn16-64.decode
insn16.decode
insn32-64.decode target/riscv: Allow generating hlv/hlvx/hsv instructions 2020-08-25 09:11:35 -07:00
insn32.decode target/riscv: Allow generating hlv/hlvx/hsv instructions 2020-08-25 09:11:35 -07:00
instmap.h
internals.h target/riscv: Check nanboxed inputs to fp helpers 2020-08-21 22:37:55 -07:00
meson.build
monitor.c
op_helper.c target/riscv: Support the Virtual Instruction fault 2020-08-25 09:11:36 -07:00
pmp.c target/riscv: Change the TLB page size depends on PMP entries. 2020-08-21 22:37:55 -07:00
pmp.h target/riscv: Change the TLB page size depends on PMP entries. 2020-08-21 22:37:55 -07:00
trace-events trace-events: Fix attribution of trace points to source 2020-09-09 17:17:58 +01:00
trace.h
translate.c target/riscv: Update the Hypervisor trap return/entry 2020-08-25 09:11:36 -07:00
vector_helper.c softfloat: Implement the full set of comparisons for float16 2020-08-28 10:48:07 -07:00