74dbf824a1
Add support for the CP0_EBase.WG bit, which allows upper bits to be written (bits 31:30 on MIPS32, or bits 63:30 on MIPS64), along with the CP0_Config5.CV bit to control whether the exception vector for Cache Error exceptions is forced into KSeg1. This is necessary on MIPS32 to support Segmentation Control and Enhanced Virtual Addressing (EVA) extensions (where KSeg1 addresses may not represent an unmapped uncached segment). It is also useful on MIPS64 to allow the exception base to reside in XKPhys, and possibly out of range of KSEG0 and KSEG1. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Yongbok Kim <yongbok.kim@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com> [yongbok.kim@imgtec.com: minor changes] Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> |
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| .. | ||
| Makefile.objs | ||
| TODO | ||
| cpu-qom.h | ||
| cpu.c | ||
| cpu.h | ||
| dsp_helper.c | ||
| gdbstub.c | ||
| helper.c | ||
| helper.h | ||
| kvm.c | ||
| kvm_mips.h | ||
| lmi_helper.c | ||
| machine.c | ||
| mips-defs.h | ||
| mips-semi.c | ||
| msa_helper.c | ||
| op_helper.c | ||
| trace-events | ||
| translate.c | ||
| translate_init.c | ||