James Hogan 74dbf824a1 target/mips: Add CP0_Ebase.WG (write gate) support ... Add support for the CP0_EBase.WG bit, which allows upper bits to be written (bits 31:30 on MIPS32, or bits 63:30 on MIPS64), along with the CP0_Config5.CV bit to control whether the exception vector for Cache Error exceptions is forced into KSeg1. This is necessary on MIPS32 to support Segmentation Control and Enhanced Virtual Addressing (EVA) extensions (where KSeg1 addresses may not represent an unmapped uncached segment). It is also useful on MIPS64 to allow the exception base to reside in XKPhys, and possibly out of range of KSEG0 and KSEG1. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Yongbok Kim <yongbok.kim@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com> [yongbok.kim@imgtec.com: minor changes] Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>		2017-07-20 22:42:26 +01:00
..
cpu-qom.h
cpu.c	qom/cpu: move tlb_flush to cpu_common_reset	2017-01-13 14:24:31 +00:00
cpu.h	target/mips: Add CP0_Ebase.WG (write gate) support	2017-07-20 22:42:26 +01:00
dsp_helper.c
gdbstub.c
helper.c	target/mips: Add CP0_Ebase.WG (write gate) support	2017-07-20 22:42:26 +01:00
helper.h	target-mips: Use clz opcode	2017-01-10 08:06:11 -08:00
kvm_mips.h
kvm.c	vcpu_dirty: share the same field in CPUState for all accelerators	2017-07-04 14:30:03 +02:00
lmi_helper.c
machine.c	target/mips: Add CP0_Ebase.WG (write gate) support	2017-07-20 22:42:26 +01:00
Makefile.objs
mips-defs.h
mips-semi.c
msa_helper.c
op_helper.c	target/mips: Add CP0_Ebase.WG (write gate) support	2017-07-20 22:42:26 +01:00
TODO
trace-events	target-mips: replace few LOG_DISAS() with trace points	2017-03-20 11:06:32 +00:00
translate_init.c	target/mips: Add CP0_Ebase.WG (write gate) support	2017-07-20 22:42:26 +01:00
translate.c	target/mips: Add CP0_Ebase.WG (write gate) support	2017-07-20 22:42:26 +01:00