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qemu-e2k/target/riscv
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LIU Zhiwei 751538d5da target/riscv: add vector stride load and store instructions 
Vector strided operations access the first memory element at the base address,
and then access subsequent elements at address increments given by the byte
offset contained in the x register specified by rs2.

Vector unit-stride operations access elements stored contiguously in memory
starting from the base effective address. It can been seen as a special
case of strided operations.

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20200701152549.1218-7-zhiwei_liu@c-sky.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 		2020-07-02 09:19:32 -07:00
..
insn_trans target/riscv: add vector stride load and store instructions 2020-07-02 09:19:32 -07:00
Makefile.objs target/riscv: add vector configure instruction 2020-07-02 09:19:32 -07:00
cpu-param.h tcg: Split out target/arch/cpu-param.h 2019-06-10 07:03:34 -07:00
cpu.c target/riscv: implementation-defined constant parameters 2020-07-02 09:19:32 -07:00
cpu.h target/riscv: add vector configure instruction 2020-07-02 09:19:32 -07:00
cpu_bits.h target/riscv: support vector extension csr 2020-07-02 09:19:32 -07:00
cpu_helper.c target/riscv: Report errors validating 2nd-stage PTEs 2020-06-19 08:24:07 -07:00
cpu_user.h Supply missing header guards 2019-06-12 13:20:21 +02:00
csr.c target/riscv: support vector extension csr 2020-07-02 09:19:32 -07:00
fpu_helper.c target/riscv: rationalise softfloat includes 2019-08-19 12:07:13 +01:00
gdbstub.c gdbstub: extend GByteArray to read register helpers 2020-03-17 17:38:38 +00:00
helper.h target/riscv: add vector stride load and store instructions 2020-07-02 09:19:32 -07:00
insn16-32.decode target/riscv: Split RVC32 and RVC64 insns into separate files 2019-05-24 12:09:22 -07:00
insn16-64.decode target/riscv: Add checks for several RVC reserved operands 2019-05-24 12:09:25 -07:00
insn16.decode target/riscv: Add checks for several RVC reserved operands 2019-05-24 12:09:25 -07:00
insn32-64.decode target/riscv: Convert RV64D insns to decodetree 2019-03-13 10:34:06 +01:00
insn32.decode target/riscv: add vector stride load and store instructions 2020-07-02 09:19:32 -07:00
instmap.h target/riscv: progressively load the instruction during decode 2020-02-25 20:20:23 +00:00
internals.h target/riscv: add vector stride load and store instructions 2020-07-02 09:19:32 -07:00
monitor.c target/riscv: Drop support for ISA spec version 1.09.1 2020-06-03 09:11:51 -07:00
op_helper.c target/riscv: Implement checks for hfence 2020-06-19 08:24:07 -07:00
pmp.c target/riscv: Use a smaller guess size for no-MMU PMP 2020-06-19 08:24:07 -07:00
pmp.h RISC-V: Check for the effective memory privilege mode during PMP checks 2019-06-23 23:44:41 -07:00
trace-events target/riscv/pmp: Convert qemu_log_mask(LOG_TRACE) to trace events 2019-09-17 08:42:42 -07:00
translate.c target/riscv: add vector stride load and store instructions 2020-07-02 09:19:32 -07:00
vector_helper.c target/riscv: add vector stride load and store instructions 2020-07-02 09:19:32 -07:00