Rob Bradford 755b41d09f target/riscv: Propagate error from PMU setup ... More closely follow the QEMU style by returning an Error and propagating it there is an error relating to the PMU setup. Further simplify the function by removing the num_counters parameter as this is available from the passed in cpu pointer. Signed-off-by: Rob Bradford <rbradford@rivosinc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Atish Patra <atishp@rivosinc.com> Message-ID: <20231031154000.18134-2-rbradford@rivosinc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2023-11-07 11:06:02 +10:00
..
insn_trans	target/riscv: Replace Zvbb checking by Zvkb	2023-11-07 11:06:02 +10:00
kvm	target/riscv/kvm: add zicsr, zifencei, zba, zbs, svnapot	2023-11-07 11:06:02 +10:00
tcg	target/riscv: Propagate error from PMU setup	2023-11-07 11:06:02 +10:00
arch_dump.c	target/riscv: Fix format for comments	2023-05-05 10:49:50 +10:00
bitmanip_helper.c	target/riscv: rvk: add support for zbkx extension	2022-04-29 10:47:45 +10:00
common-semi-target.h	semihosting: Split out common-semi-target.h	2022-06-28 04:35:07 +05:30
cpu_bits.h	target/riscv: Add M-mode virtual interrupt and IRQ filtering support.	2023-11-07 11:02:17 +10:00
cpu_cfg.h	target/riscv: Add cfg properties for Zvks[c|g] extensions	2023-11-07 11:06:02 +10:00
cpu_helper.c	target/riscv: Add HS-mode virtual interrupt and IRQ filtering support.	2023-11-07 11:02:17 +10:00
cpu_user.h
cpu_vendorid.h	target/riscv: add Ventana's Veyron V1 CPU	2023-05-05 10:49:50 +10:00
cpu-param.h	target/riscv: Remove NB_MMU_MODES define	2023-03-13 06:44:37 -07:00
cpu-qom.h	target/riscv: add 'max' CPU type	2023-10-12 11:39:33 +10:00
cpu.c	target/riscv: cpu: Set the OpenTitan priv to 1.12.0	2023-11-07 11:06:02 +10:00
cpu.h	target/riscv: add riscv_cpu_accelerator_compatible()	2023-11-07 11:06:02 +10:00
crypto_helper.c	target/riscv: Use accelerated helper for AES64KS1I	2023-09-11 11:45:55 +10:00
csr.c	target/riscv: correct csr_ops[CSR_MSECCFG]	2023-11-07 11:06:02 +10:00
debug.c	target/riscv: Allocate itrigger timers only once	2023-09-11 11:45:55 +10:00
debug.h	target/riscv: Allocate itrigger timers only once	2023-09-11 11:45:55 +10:00
fpu_helper.c	riscv: Add support for the Zfa extension	2023-07-10 22:29:20 +10:00
gdbstub.c	target/riscv: rename ext_icsr to ext_zicsr	2023-11-07 11:02:17 +10:00
helper.h	target/riscv: Add Zvksed ISA extension support	2023-09-11 11:45:55 +10:00
insn16.decode	target/riscv: add support for Zcmt extension	2023-05-05 10:49:50 +10:00
insn32.decode	target/riscv: Add Zvksed ISA extension support	2023-09-11 11:45:55 +10:00
instmap.h	target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt()	2022-09-07 09:18:32 +02:00
internals.h	target/riscv: Introduce mmuidx_2stage	2023-05-05 10:49:50 +10:00
Kconfig
m128_helper.c	target/helpers: Remove unnecessary 'qemu/main-loop.h' header	2023-08-31 19:47:43 +02:00
machine.c	target/riscv: Add HS-mode virtual interrupt and IRQ filtering support.	2023-11-07 11:02:17 +10:00
meson.build	target/riscv: move KVM only files to kvm subdir	2023-10-12 12:20:24 +10:00
monitor.c	riscv: spelling fixes	2023-09-08 13:08:52 +03:00
op_helper.c	target/helpers: Remove unnecessary 'qemu/main-loop.h' header	2023-08-31 19:47:43 +02:00
pmp.c	target/riscv: pmp: Ignore writes when RW=01	2023-11-07 11:06:02 +10:00
pmp.h	target/riscv: pmp: Clear pmp/smepmp bits on reset	2023-11-07 11:06:02 +10:00
pmu.c	target/riscv: Propagate error from PMU setup	2023-11-07 11:06:02 +10:00
pmu.h	target/riscv: Propagate error from PMU setup	2023-11-07 11:06:02 +10:00
riscv-qmp-cmds.c	target/riscv/riscv-qmp-cmds.c: check CPU accel in query-cpu-model-expansion	2023-11-07 11:06:02 +10:00
sbi_ecall_interface.h	target/riscv: Fix format for comments	2023-05-05 10:49:50 +10:00
time_helper.c	target/riscv: Simplify type conversion for CPURISCVState	2023-05-05 10:49:49 +10:00
time_helper.h	target/riscv: Simplify type conversion for CPURISCVState	2023-05-05 10:49:49 +10:00
trace-events
trace.h
translate.c	accel/tcg: Replace CPUState.env_ptr with cpu_env()	2023-10-04 11:03:54 -07:00
vcrypto_helper.c	target/riscv: Add Zvksed ISA extension support	2023-09-11 11:45:55 +10:00
vector_helper.c	target/riscv: Fix vfwmaccbf16.vf	2023-10-12 12:50:13 +10:00
vector_internals.c	target/riscv: Refactor some of the generic vector functionality	2023-09-11 11:45:54 +10:00
vector_internals.h	target/riscv: Refactor some of the generic vector functionality	2023-09-11 11:45:55 +10:00
xthead.decode	RISC-V: Adding XTheadFmv ISA extension	2023-02-07 08:19:23 +10:00
XVentanaCondOps.decode	target/riscv: Add XVentanaCondOps custom extension	2022-02-16 12:24:18 +10:00
zce_helper.c	target/riscv: add support for Zcmt extension	2023-05-05 10:49:50 +10:00