b8fb878aa2
The RISC-V ACLINT is more modular and backward compatible with original SiFive CLINT so instead of duplicating the original SiFive CLINT implementation we upgrade the current SiFive CLINT implementation to RISC-V ACLINT implementation. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-id: 20210831110603.338681-3-anup.patel@wdc.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
81 lines
2.4 KiB
C
81 lines
2.4 KiB
C
/*
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* RISC-V ACLINT (Advanced Core Local Interruptor) interface
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*
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* Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
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* Copyright (c) 2017 SiFive, Inc.
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* Copyright (c) 2021 Western Digital Corporation or its affiliates.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef HW_RISCV_ACLINT_H
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#define HW_RISCV_ACLINT_H
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#include "hw/sysbus.h"
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#define TYPE_RISCV_ACLINT_MTIMER "riscv.aclint.mtimer"
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#define RISCV_ACLINT_MTIMER(obj) \
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OBJECT_CHECK(RISCVAclintMTimerState, (obj), TYPE_RISCV_ACLINT_MTIMER)
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typedef struct RISCVAclintMTimerState {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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MemoryRegion mmio;
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uint32_t hartid_base;
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uint32_t num_harts;
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uint32_t timecmp_base;
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uint32_t time_base;
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uint32_t aperture_size;
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uint32_t timebase_freq;
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qemu_irq *timer_irqs;
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} RISCVAclintMTimerState;
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DeviceState *riscv_aclint_mtimer_create(hwaddr addr, hwaddr size,
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uint32_t hartid_base, uint32_t num_harts,
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uint32_t timecmp_base, uint32_t time_base, uint32_t timebase_freq,
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bool provide_rdtime);
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#define TYPE_RISCV_ACLINT_SWI "riscv.aclint.swi"
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#define RISCV_ACLINT_SWI(obj) \
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OBJECT_CHECK(RISCVAclintSwiState, (obj), TYPE_RISCV_ACLINT_SWI)
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typedef struct RISCVAclintSwiState {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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MemoryRegion mmio;
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uint32_t hartid_base;
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uint32_t num_harts;
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uint32_t sswi;
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qemu_irq *soft_irqs;
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} RISCVAclintSwiState;
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DeviceState *riscv_aclint_swi_create(hwaddr addr, uint32_t hartid_base,
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uint32_t num_harts, bool sswi);
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enum {
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RISCV_ACLINT_DEFAULT_MTIMECMP = 0x0,
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RISCV_ACLINT_DEFAULT_MTIME = 0x7ff8,
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RISCV_ACLINT_DEFAULT_MTIMER_SIZE = 0x8000,
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RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ = 10000000,
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RISCV_ACLINT_MAX_HARTS = 4095,
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RISCV_ACLINT_SWI_SIZE = 0x4000
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};
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#endif
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