75a6ed875f
riscv_sifive_e_soc_init(), riscv_sifive_u_soc_init(),
spike_board_init(), spike_v1_10_0_board_init(),
spike_v1_09_1_board_init(), and riscv_virt_board_init() create
"riscv-hart_array" sysbus devices in a way that leaves them unplugged.
Create them the common way that puts them into the main system bus.
Affects machines sifive_e, sifive_u, spike, spike_v1.10, spike_v1.9.1,
and virt. Visible in "info qtree", here's the change for sifive_e:
bus: main-system-bus
type System
+ dev: riscv.hart_array, id ""
+ num-harts = 1 (0x1)
+ hartid-base = 0 (0x0)
+ cpu-type = "sifive-e31-riscv-cpu"
dev: sifive_soc.gpio, id ""
Cc: Palmer Dabbelt <palmer@dabbelt.com>
Cc: Alistair Francis <Alistair.Francis@wdc.com>
Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Cc: qemu-riscv@nongnu.org
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20200609122339.937862-20-armbru@redhat.com>
184 lines
7.3 KiB
C
184 lines
7.3 KiB
C
/*
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* QEMU RISC-V Board Compatible with OpenTitan FPGA platform
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*
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* Copyright (c) 2020 Western Digital
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*
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* Provides a board compatible with the OpenTitan FPGA platform:
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "hw/riscv/opentitan.h"
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#include "qapi/error.h"
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#include "hw/boards.h"
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#include "hw/misc/unimp.h"
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#include "hw/riscv/boot.h"
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#include "exec/address-spaces.h"
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static const struct MemmapEntry {
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hwaddr base;
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hwaddr size;
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} ibex_memmap[] = {
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[IBEX_ROM] = { 0x00008000, 0xc000 },
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[IBEX_RAM] = { 0x10000000, 0x10000 },
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[IBEX_FLASH] = { 0x20000000, 0x80000 },
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[IBEX_UART] = { 0x40000000, 0x10000 },
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[IBEX_GPIO] = { 0x40010000, 0x10000 },
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[IBEX_SPI] = { 0x40020000, 0x10000 },
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[IBEX_FLASH_CTRL] = { 0x40030000, 0x10000 },
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[IBEX_PINMUX] = { 0x40070000, 0x10000 },
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[IBEX_RV_TIMER] = { 0x40080000, 0x10000 },
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[IBEX_PLIC] = { 0x40090000, 0x10000 },
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[IBEX_PWRMGR] = { 0x400A0000, 0x10000 },
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[IBEX_RSTMGR] = { 0x400B0000, 0x10000 },
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[IBEX_CLKMGR] = { 0x400C0000, 0x10000 },
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[IBEX_AES] = { 0x40110000, 0x10000 },
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[IBEX_HMAC] = { 0x40120000, 0x10000 },
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[IBEX_ALERT_HANDLER] = { 0x40130000, 0x10000 },
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[IBEX_NMI_GEN] = { 0x40140000, 0x10000 },
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[IBEX_USBDEV] = { 0x40150000, 0x10000 },
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[IBEX_PADCTRL] = { 0x40160000, 0x10000 }
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};
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static void riscv_opentitan_init(MachineState *machine)
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{
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const struct MemmapEntry *memmap = ibex_memmap;
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OpenTitanState *s = g_new0(OpenTitanState, 1);
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MemoryRegion *sys_mem = get_system_memory();
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MemoryRegion *main_mem = g_new(MemoryRegion, 1);
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/* Initialize SoC */
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object_initialize_child(OBJECT(machine), "soc", &s->soc,
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sizeof(s->soc), TYPE_RISCV_IBEX_SOC,
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&error_abort, NULL);
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object_property_set_bool(OBJECT(&s->soc), true, "realized",
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&error_abort);
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memory_region_init_ram(main_mem, NULL, "riscv.lowrisc.ibex.ram",
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memmap[IBEX_RAM].size, &error_fatal);
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memory_region_add_subregion(sys_mem,
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memmap[IBEX_RAM].base, main_mem);
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if (machine->firmware) {
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riscv_load_firmware(machine->firmware, memmap[IBEX_RAM].base, NULL);
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}
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if (machine->kernel_filename) {
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riscv_load_kernel(machine->kernel_filename, NULL);
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}
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}
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static void riscv_opentitan_machine_init(MachineClass *mc)
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{
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mc->desc = "RISC-V Board compatible with OpenTitan";
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mc->init = riscv_opentitan_init;
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mc->max_cpus = 1;
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mc->default_cpu_type = TYPE_RISCV_CPU_IBEX;
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}
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DEFINE_MACHINE("opentitan", riscv_opentitan_machine_init)
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static void riscv_lowrisc_ibex_soc_init(Object *obj)
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{
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LowRISCIbexSoCState *s = RISCV_IBEX_SOC(obj);
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sysbus_init_child_obj(obj, "cpus", &s->cpus,
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sizeof(s->cpus), TYPE_RISCV_HART_ARRAY);
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}
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static void riscv_lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
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{
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const struct MemmapEntry *memmap = ibex_memmap;
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MachineState *ms = MACHINE(qdev_get_machine());
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LowRISCIbexSoCState *s = RISCV_IBEX_SOC(dev_soc);
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MemoryRegion *sys_mem = get_system_memory();
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object_property_set_str(OBJECT(&s->cpus), ms->cpu_type, "cpu-type",
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&error_abort);
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object_property_set_int(OBJECT(&s->cpus), ms->smp.cpus, "num-harts",
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&error_abort);
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object_property_set_bool(OBJECT(&s->cpus), true, "realized",
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&error_abort);
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/* Boot ROM */
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memory_region_init_rom(&s->rom, OBJECT(dev_soc), "riscv.lowrisc.ibex.rom",
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memmap[IBEX_ROM].size, &error_fatal);
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memory_region_add_subregion(sys_mem,
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memmap[IBEX_ROM].base, &s->rom);
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/* Flash memory */
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memory_region_init_rom(&s->flash_mem, OBJECT(dev_soc), "riscv.lowrisc.ibex.flash",
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memmap[IBEX_FLASH].size, &error_fatal);
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memory_region_add_subregion(sys_mem, memmap[IBEX_FLASH].base,
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&s->flash_mem);
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create_unimplemented_device("riscv.lowrisc.ibex.uart",
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memmap[IBEX_UART].base, memmap[IBEX_UART].size);
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create_unimplemented_device("riscv.lowrisc.ibex.gpio",
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memmap[IBEX_GPIO].base, memmap[IBEX_GPIO].size);
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create_unimplemented_device("riscv.lowrisc.ibex.spi",
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memmap[IBEX_SPI].base, memmap[IBEX_SPI].size);
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create_unimplemented_device("riscv.lowrisc.ibex.flash_ctrl",
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memmap[IBEX_FLASH_CTRL].base, memmap[IBEX_FLASH_CTRL].size);
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create_unimplemented_device("riscv.lowrisc.ibex.rv_timer",
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memmap[IBEX_RV_TIMER].base, memmap[IBEX_RV_TIMER].size);
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create_unimplemented_device("riscv.lowrisc.ibex.pwrmgr",
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memmap[IBEX_PWRMGR].base, memmap[IBEX_PWRMGR].size);
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create_unimplemented_device("riscv.lowrisc.ibex.rstmgr",
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memmap[IBEX_RSTMGR].base, memmap[IBEX_RSTMGR].size);
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create_unimplemented_device("riscv.lowrisc.ibex.clkmgr",
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memmap[IBEX_CLKMGR].base, memmap[IBEX_CLKMGR].size);
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create_unimplemented_device("riscv.lowrisc.ibex.aes",
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memmap[IBEX_AES].base, memmap[IBEX_AES].size);
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create_unimplemented_device("riscv.lowrisc.ibex.hmac",
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memmap[IBEX_HMAC].base, memmap[IBEX_HMAC].size);
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create_unimplemented_device("riscv.lowrisc.ibex.plic",
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memmap[IBEX_PLIC].base, memmap[IBEX_PLIC].size);
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create_unimplemented_device("riscv.lowrisc.ibex.pinmux",
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memmap[IBEX_PINMUX].base, memmap[IBEX_PINMUX].size);
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create_unimplemented_device("riscv.lowrisc.ibex.alert_handler",
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memmap[IBEX_ALERT_HANDLER].base, memmap[IBEX_ALERT_HANDLER].size);
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create_unimplemented_device("riscv.lowrisc.ibex.nmi_gen",
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memmap[IBEX_NMI_GEN].base, memmap[IBEX_NMI_GEN].size);
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create_unimplemented_device("riscv.lowrisc.ibex.usbdev",
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memmap[IBEX_USBDEV].base, memmap[IBEX_USBDEV].size);
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create_unimplemented_device("riscv.lowrisc.ibex.padctrl",
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memmap[IBEX_PADCTRL].base, memmap[IBEX_PADCTRL].size);
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}
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static void riscv_lowrisc_ibex_soc_class_init(ObjectClass *oc, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(oc);
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dc->realize = riscv_lowrisc_ibex_soc_realize;
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/* Reason: Uses serial_hds in realize function, thus can't be used twice */
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dc->user_creatable = false;
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}
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static const TypeInfo riscv_lowrisc_ibex_soc_type_info = {
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.name = TYPE_RISCV_IBEX_SOC,
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.parent = TYPE_DEVICE,
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.instance_size = sizeof(LowRISCIbexSoCState),
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.instance_init = riscv_lowrisc_ibex_soc_init,
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.class_init = riscv_lowrisc_ibex_soc_class_init,
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};
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static void riscv_lowrisc_ibex_soc_register_types(void)
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{
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type_register_static(&riscv_lowrisc_ibex_soc_type_info);
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}
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type_init(riscv_lowrisc_ibex_soc_register_types)
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