qemu-e2k/include/fpu
Richard Henderson 27ae5109a2 softfloat: Specialize udiv_qrnnd for ppc64
The ISA has a 128/64-bit division instruction, though it assumes the
low 64-bits of the numerator are 0, and so requires a bit more fixup
than a full 128-bit division insn.

Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-10-05 12:57:41 -05:00
..
softfloat-macros.h softfloat: Specialize udiv_qrnnd for ppc64 2018-10-05 12:57:41 -05:00
softfloat-types.h
softfloat.h softfloat: remove float64_trunc_to_int 2018-10-05 12:57:41 -05:00