fe73674af1
Export the igb_vf_reset() helper routine from the PF model to let the IGBVF model implement its own device reset. Cc: Akihiko Odaki <akihiko.odaki@daynix.com> Suggested-by: Sriram Yagnaraman <sriram.yagnaraman@est.tech> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Cédric Le Goater <clg@redhat.com> Signed-off-by: Jason Wang <jasowang@redhat.com>
149 lines
3.6 KiB
C
149 lines
3.6 KiB
C
/*
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* Core code for QEMU igb emulation
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*
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* Datasheet:
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* https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/82576eg-gbe-datasheet.pdf
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*
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* Copyright (c) 2020-2023 Red Hat, Inc.
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* Copyright (c) 2015 Ravello Systems LTD (http://ravellosystems.com)
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* Developed by Daynix Computing LTD (http://www.daynix.com)
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*
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* Authors:
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* Akihiko Odaki <akihiko.odaki@daynix.com>
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* Gal Hammmer <gal.hammer@sap.com>
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* Marcel Apfelbaum <marcel.apfelbaum@gmail.com>
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* Dmitry Fleytman <dmitry@daynix.com>
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* Leonid Bloch <leonid@daynix.com>
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* Yan Vugenfirer <yan@daynix.com>
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*
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* Based on work done by:
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* Nir Peleg, Tutis Systems Ltd. for Qumranet Inc.
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* Copyright (c) 2008 Qumranet
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* Based on work done by:
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* Copyright (c) 2007 Dan Aloni
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* Copyright (c) 2004 Antony T Curtis
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef HW_NET_IGB_CORE_H
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#define HW_NET_IGB_CORE_H
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#define E1000E_MAC_SIZE (0x8000)
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#define IGB_EEPROM_SIZE (1024)
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#define IGB_INTR_NUM (25)
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#define IGB_MSIX_VEC_NUM (10)
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#define IGBVF_MSIX_VEC_NUM (3)
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#define IGB_NUM_QUEUES (16)
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#define IGB_NUM_VM_POOLS (8)
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typedef struct IGBCore IGBCore;
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enum { PHY_R = BIT(0),
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PHY_W = BIT(1),
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PHY_RW = PHY_R | PHY_W };
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typedef struct IGBIntrDelayTimer_st {
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QEMUTimer *timer;
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bool running;
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uint32_t delay_reg;
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uint32_t delay_resolution_ns;
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IGBCore *core;
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} IGBIntrDelayTimer;
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struct IGBCore {
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uint32_t mac[E1000E_MAC_SIZE];
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uint16_t phy[MAX_PHY_REG_ADDRESS + 1];
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uint16_t eeprom[IGB_EEPROM_SIZE];
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uint8_t rx_desc_len;
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QEMUTimer *autoneg_timer;
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struct igb_tx {
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struct e1000_adv_tx_context_desc ctx[2];
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uint32_t first_cmd_type_len;
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uint32_t first_olinfo_status;
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bool first;
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bool skip_cp;
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struct NetTxPkt *tx_pkt;
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} tx[IGB_NUM_QUEUES];
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struct NetRxPkt *rx_pkt;
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bool has_vnet;
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int max_queue_num;
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IGBIntrDelayTimer eitr[IGB_INTR_NUM];
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VMChangeStateEntry *vmstate;
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uint32_t eitr_guest_value[IGB_INTR_NUM];
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uint8_t permanent_mac[ETH_ALEN];
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NICState *owner_nic;
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PCIDevice *owner;
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void (*owner_start_recv)(PCIDevice *d);
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int64_t timadj;
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};
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void
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igb_core_write(IGBCore *core, hwaddr addr, uint64_t val, unsigned size);
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uint64_t
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igb_core_read(IGBCore *core, hwaddr addr, unsigned size);
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void
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igb_core_pci_realize(IGBCore *regs,
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const uint16_t *eeprom_templ,
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uint32_t eeprom_size,
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const uint8_t *macaddr);
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void
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igb_core_reset(IGBCore *core);
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void
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igb_core_pre_save(IGBCore *core);
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int
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igb_core_post_load(IGBCore *core);
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void
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igb_core_set_link_status(IGBCore *core);
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void
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igb_core_pci_uninit(IGBCore *core);
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void
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igb_core_vf_reset(IGBCore *core, uint16_t vfn);
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bool
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igb_can_receive(IGBCore *core);
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ssize_t
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igb_receive(IGBCore *core, const uint8_t *buf, size_t size);
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ssize_t
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igb_receive_iov(IGBCore *core, const struct iovec *iov, int iovcnt);
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void
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igb_start_recv(IGBCore *core);
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#endif
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