Peter Maydell
7721a30442
----------------------------------------------------------------
target-arm queue: * support -bios option in vexpress boards * register the Cortex-A57 impdef system registers * fix handling of UXN bit in ARMv8 page tables * complete support of crypto insns in A32/T32 * implement CRC and crypto insns in A64 * fix bugs in generic timer control register ---------------------------------------------------------------- -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQIcBAABCAAGBQJTlc3qAAoJEDwlJe0UNgzeZYsP/18PXMyDjeP7yl/kFXJ3YJ/E XdulZM3tYm7SA1PhgKKt3apCpL8lNhvlckjdbERT3+Pr4HaxOFEz1IkAu0fjrYOl Vq1c3H5N4iLpfJMhNl/iB4JQ+9UgWv1THet0sfgAOFto1vGlUADRMLZVoZbPiPO8 +Zs0wKKyWoj1kKcZ7cVsp+hN+GDe5YtH3HM6io7ZzJWgSkVHgbkP4a7kYdkOSQUb x88pfm7Xn4LuerupDFQLBuT3CVcpWbd8aOWp2BqUG913xFkK4lVstSIF7jLm4hnR k/1Yiw/OFGCHmFIV8ABF2fw5YSB3iJ/RVKG01Rlac67Z9OzhySa4ssJ0JHjY+Wzd L8mE5upUZZNvpUg1K5x7cy8/AYVlx8erWfteqGcmrYJqaAKek6+ySHiqf2ZsdZzk C9OP3i/BHUlowP2P29VcWnj8R1a6pljXxqkIhu1GPkkZ09o1NWxEm7RxkLBij2Vp sObuTJgg3rWnZ/DmGjDg3u1OwlRz+JRyadKwhPeZ5ZqESqqT3O+OOh8H76e/HG4F Y5PXXEtPK0v/bttkvtv4GTJcNiHLtgYrF6+Mw+3xi7SNE15vvY1zop1csMLaLafT DUf9rcbUPBKY/8kFXXWEUWm01mgB7t0MlrVK9AFwSEoYHc9xox5fpsKswwRXVQ+6 RH0wdjFMVCa58JQuqcOc =bdN6 -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20140609-1' into staging ---------------------------------------------------------------- target-arm queue: * support -bios option in vexpress boards * register the Cortex-A57 impdef system registers * fix handling of UXN bit in ARMv8 page tables * complete support of crypto insns in A32/T32 * implement CRC and crypto insns in A64 * fix bugs in generic timer control register ---------------------------------------------------------------- # gpg: Signature made Mon 09 Jun 2014 16:08:26 BST using RSA key ID 14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" * remotes/pmaydell/tags/pull-target-arm-20140609-1: target-arm: Delete unused iwmmxt_msadb helper target-arm: Fix errors in writes to generic timer control registers target-arm: A64: Implement two-register SHA instructions target-arm: A64: Implement 3-register SHA instructions target-arm: A64: Implement AES instructions target-arm: A32/T32: Mask CRC value in calling code, not helper target-arm: A64: Implement CRC instructions target-arm: VFPv4 implies half-precision extension target-arm: Clean up handling of ARMv8 optional feature bits target-arm: Remove unnecessary setting of feature bits target-arm: arm_any_initfn() should never set ARM_FEATURE_AARCH64 target-arm: A64: Use PMULL feature bit for PMULL target-arm: add support for v8 VMULL.P64 instruction target-arm: Allow 3reg_wide undefreq to encode more bad size options target-arm: add support for v8 SHA1 and SHA256 instructions target-arm: Correct handling of UXN bit in ARMv8 LPAE page tables target-arm: Prepare cpreg writefns/readfns for EL3/SecExt target-arm/cpu64.c: Actually register Cortex-A57 impdef registers vexpress: Add support for the -bios flag to provide firmware Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
…
…
…
…
…
…
Read the documentation in qemu-doc.html or on http://wiki.qemu-project.org - QEMU team
Description
Languages
C
83.1%
C++
6.3%
Python
3.2%
Dylan
2.8%
Shell
1.6%
Other
2.8%