Peter Maydell 7721a30442 ----------------------------------------------------------------
target-arm queue:
  * support -bios option in vexpress boards
  * register the Cortex-A57 impdef system registers
  * fix handling of UXN bit in ARMv8 page tables
  * complete support of crypto insns in A32/T32
  * implement CRC and crypto insns in A64
  * fix bugs in generic timer control register
 
 ----------------------------------------------------------------
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Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20140609-1' into staging

----------------------------------------------------------------
target-arm queue:
 * support -bios option in vexpress boards
 * register the Cortex-A57 impdef system registers
 * fix handling of UXN bit in ARMv8 page tables
 * complete support of crypto insns in A32/T32
 * implement CRC and crypto insns in A64
 * fix bugs in generic timer control register

----------------------------------------------------------------

# gpg: Signature made Mon 09 Jun 2014 16:08:26 BST using RSA key ID 14360CDE
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>"

* remotes/pmaydell/tags/pull-target-arm-20140609-1:
  target-arm: Delete unused iwmmxt_msadb helper
  target-arm: Fix errors in writes to generic timer control registers
  target-arm: A64: Implement two-register SHA instructions
  target-arm: A64: Implement 3-register SHA instructions
  target-arm: A64: Implement AES instructions
  target-arm: A32/T32: Mask CRC value in calling code, not helper
  target-arm: A64: Implement CRC instructions
  target-arm: VFPv4 implies half-precision extension
  target-arm: Clean up handling of ARMv8 optional feature bits
  target-arm: Remove unnecessary setting of feature bits
  target-arm: arm_any_initfn() should never set ARM_FEATURE_AARCH64
  target-arm: A64: Use PMULL feature bit for PMULL
  target-arm: add support for v8 VMULL.P64 instruction
  target-arm: Allow 3reg_wide undefreq to encode more bad size options
  target-arm: add support for v8 SHA1 and SHA256 instructions
  target-arm: Correct handling of UXN bit in ARMv8 LPAE page tables
  target-arm: Prepare cpreg writefns/readfns for EL3/SecExt
  target-arm/cpu64.c: Actually register Cortex-A57 impdef registers
  vexpress: Add support for the -bios flag to provide firmware

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-06-09 17:04:13 +01:00
2014-06-09 15:43:40 +02:00
2014-06-09 11:54:22 +01:00
2014-05-20 13:05:58 +02:00
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2014-05-19 11:36:48 +02:00
2014-06-02 16:49:00 +02:00
2014-06-09 15:43:40 +02:00
2014-06-05 16:10:33 +02:00
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2014-03-12 17:26:32 +01:00
2013-09-05 09:40:31 -05:00
2014-06-09 15:43:40 +02:00
2013-10-11 09:34:56 -07:00
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2013-08-12 09:15:12 -05:00
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2014-06-05 16:10:33 +02:00
2014-05-24 00:07:29 +04:00
2014-03-13 14:34:16 +00:00
2014-02-25 14:30:28 +01:00
2014-05-28 17:36:21 +02:00
2014-04-18 10:33:36 +04:00
2014-06-04 11:30:32 +02:00
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2014-05-24 00:07:29 +04:00
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2014-06-02 17:07:21 +01:00
2014-06-05 16:10:33 +02:00
2014-04-17 20:39:32 +01:00
2013-10-11 09:34:56 -07:00
2014-06-09 15:43:40 +02:00
2014-05-07 16:16:43 +00:00

Read the documentation in qemu-doc.html or on http://wiki.qemu-project.org

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