995 lines
28 KiB
C
995 lines
28 KiB
C
/*
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* QEMU PowerPC 4xx embedded processors shared devices emulation
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*
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* Copyright (c) 2007 Jocelyn Mayer
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "qemu/osdep.h"
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#include "qemu/units.h"
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#include "sysemu/reset.h"
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#include "cpu.h"
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#include "hw/irq.h"
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#include "hw/ppc/ppc.h"
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#include "hw/ppc/ppc4xx.h"
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#include "hw/qdev-properties.h"
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#include "qemu/log.h"
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#include "exec/address-spaces.h"
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#include "qemu/error-report.h"
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#include "qapi/error.h"
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#include "trace.h"
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/*****************************************************************************/
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/* SDRAM controller */
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typedef struct ppc4xx_sdram_t ppc4xx_sdram_t;
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struct ppc4xx_sdram_t {
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uint32_t addr;
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int nbanks;
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MemoryRegion containers[4]; /* used for clipping */
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MemoryRegion *ram_memories;
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hwaddr ram_bases[4];
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hwaddr ram_sizes[4];
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uint32_t besr0;
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uint32_t besr1;
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uint32_t bear;
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uint32_t cfg;
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uint32_t status;
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uint32_t rtr;
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uint32_t pmit;
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uint32_t bcr[4];
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uint32_t tr;
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uint32_t ecccfg;
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uint32_t eccesr;
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qemu_irq irq;
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};
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enum {
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SDRAM0_CFGADDR = 0x010,
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SDRAM0_CFGDATA = 0x011,
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};
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/*
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* XXX: TOFIX: some patches have made this code become inconsistent:
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* there are type inconsistencies, mixing hwaddr, target_ulong
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* and uint32_t
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*/
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static uint32_t sdram_bcr(hwaddr ram_base, hwaddr ram_size)
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{
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uint32_t bcr;
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switch (ram_size) {
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case 4 * MiB:
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bcr = 0x00000000;
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break;
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case 8 * MiB:
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bcr = 0x00020000;
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break;
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case 16 * MiB:
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bcr = 0x00040000;
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break;
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case 32 * MiB:
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bcr = 0x00060000;
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break;
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case 64 * MiB:
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bcr = 0x00080000;
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break;
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case 128 * MiB:
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bcr = 0x000A0000;
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break;
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case 256 * MiB:
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bcr = 0x000C0000;
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: invalid RAM size 0x%" HWADDR_PRIx "\n", __func__,
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ram_size);
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return 0x00000000;
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}
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bcr |= ram_base & 0xFF800000;
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bcr |= 1;
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return bcr;
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}
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static inline hwaddr sdram_base(uint32_t bcr)
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{
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return bcr & 0xFF800000;
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}
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static target_ulong sdram_size(uint32_t bcr)
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{
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target_ulong size;
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int sh;
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sh = (bcr >> 17) & 0x7;
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if (sh == 7) {
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size = -1;
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} else {
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size = (4 * MiB) << sh;
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}
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return size;
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}
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static void sdram_set_bcr(ppc4xx_sdram_t *sdram, int i,
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uint32_t bcr, int enabled)
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{
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if (sdram->bcr[i] & 0x00000001) {
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/* Unmap RAM */
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trace_ppc4xx_sdram_unmap(sdram_base(sdram->bcr[i]),
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sdram_size(sdram->bcr[i]));
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memory_region_del_subregion(get_system_memory(),
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&sdram->containers[i]);
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memory_region_del_subregion(&sdram->containers[i],
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&sdram->ram_memories[i]);
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object_unparent(OBJECT(&sdram->containers[i]));
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}
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sdram->bcr[i] = bcr & 0xFFDEE001;
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if (enabled && (bcr & 0x00000001)) {
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trace_ppc4xx_sdram_map(sdram_base(bcr), sdram_size(bcr));
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memory_region_init(&sdram->containers[i], NULL, "sdram-containers",
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sdram_size(bcr));
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memory_region_add_subregion(&sdram->containers[i], 0,
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&sdram->ram_memories[i]);
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memory_region_add_subregion(get_system_memory(),
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sdram_base(bcr),
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&sdram->containers[i]);
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}
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}
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static void sdram_map_bcr(ppc4xx_sdram_t *sdram)
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{
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int i;
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for (i = 0; i < sdram->nbanks; i++) {
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if (sdram->ram_sizes[i] != 0) {
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sdram_set_bcr(sdram, i, sdram_bcr(sdram->ram_bases[i],
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sdram->ram_sizes[i]), 1);
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} else {
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sdram_set_bcr(sdram, i, 0x00000000, 0);
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}
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}
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}
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static void sdram_unmap_bcr(ppc4xx_sdram_t *sdram)
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{
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int i;
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for (i = 0; i < sdram->nbanks; i++) {
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trace_ppc4xx_sdram_unmap(sdram_base(sdram->bcr[i]),
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sdram_size(sdram->bcr[i]));
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memory_region_del_subregion(get_system_memory(),
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&sdram->ram_memories[i]);
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}
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}
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static uint32_t dcr_read_sdram(void *opaque, int dcrn)
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{
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ppc4xx_sdram_t *sdram;
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uint32_t ret;
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sdram = opaque;
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switch (dcrn) {
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case SDRAM0_CFGADDR:
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ret = sdram->addr;
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break;
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case SDRAM0_CFGDATA:
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switch (sdram->addr) {
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case 0x00: /* SDRAM_BESR0 */
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ret = sdram->besr0;
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break;
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case 0x08: /* SDRAM_BESR1 */
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ret = sdram->besr1;
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break;
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case 0x10: /* SDRAM_BEAR */
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ret = sdram->bear;
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break;
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case 0x20: /* SDRAM_CFG */
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ret = sdram->cfg;
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break;
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case 0x24: /* SDRAM_STATUS */
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ret = sdram->status;
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break;
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case 0x30: /* SDRAM_RTR */
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ret = sdram->rtr;
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break;
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case 0x34: /* SDRAM_PMIT */
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ret = sdram->pmit;
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break;
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case 0x40: /* SDRAM_B0CR */
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ret = sdram->bcr[0];
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break;
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case 0x44: /* SDRAM_B1CR */
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ret = sdram->bcr[1];
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break;
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case 0x48: /* SDRAM_B2CR */
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ret = sdram->bcr[2];
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break;
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case 0x4C: /* SDRAM_B3CR */
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ret = sdram->bcr[3];
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break;
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case 0x80: /* SDRAM_TR */
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ret = -1; /* ? */
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break;
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case 0x94: /* SDRAM_ECCCFG */
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ret = sdram->ecccfg;
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break;
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case 0x98: /* SDRAM_ECCESR */
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ret = sdram->eccesr;
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break;
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default: /* Error */
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ret = -1;
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break;
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}
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break;
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default:
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/* Avoid gcc warning */
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ret = 0x00000000;
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break;
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}
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return ret;
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}
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static void dcr_write_sdram(void *opaque, int dcrn, uint32_t val)
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{
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ppc4xx_sdram_t *sdram;
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sdram = opaque;
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switch (dcrn) {
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case SDRAM0_CFGADDR:
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sdram->addr = val;
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break;
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case SDRAM0_CFGDATA:
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switch (sdram->addr) {
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case 0x00: /* SDRAM_BESR0 */
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sdram->besr0 &= ~val;
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break;
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case 0x08: /* SDRAM_BESR1 */
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sdram->besr1 &= ~val;
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break;
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case 0x10: /* SDRAM_BEAR */
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sdram->bear = val;
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break;
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case 0x20: /* SDRAM_CFG */
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val &= 0xFFE00000;
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if (!(sdram->cfg & 0x80000000) && (val & 0x80000000)) {
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trace_ppc4xx_sdram_enable("enable");
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/* validate all RAM mappings */
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sdram_map_bcr(sdram);
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sdram->status &= ~0x80000000;
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} else if ((sdram->cfg & 0x80000000) && !(val & 0x80000000)) {
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trace_ppc4xx_sdram_enable("disable");
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/* invalidate all RAM mappings */
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sdram_unmap_bcr(sdram);
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sdram->status |= 0x80000000;
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}
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if (!(sdram->cfg & 0x40000000) && (val & 0x40000000)) {
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sdram->status |= 0x40000000;
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} else if ((sdram->cfg & 0x40000000) && !(val & 0x40000000)) {
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sdram->status &= ~0x40000000;
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}
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sdram->cfg = val;
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break;
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case 0x24: /* SDRAM_STATUS */
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/* Read-only register */
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break;
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case 0x30: /* SDRAM_RTR */
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sdram->rtr = val & 0x3FF80000;
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break;
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case 0x34: /* SDRAM_PMIT */
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sdram->pmit = (val & 0xF8000000) | 0x07C00000;
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break;
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case 0x40: /* SDRAM_B0CR */
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sdram_set_bcr(sdram, 0, val, sdram->cfg & 0x80000000);
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break;
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case 0x44: /* SDRAM_B1CR */
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sdram_set_bcr(sdram, 1, val, sdram->cfg & 0x80000000);
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break;
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case 0x48: /* SDRAM_B2CR */
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sdram_set_bcr(sdram, 2, val, sdram->cfg & 0x80000000);
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break;
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case 0x4C: /* SDRAM_B3CR */
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sdram_set_bcr(sdram, 3, val, sdram->cfg & 0x80000000);
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break;
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case 0x80: /* SDRAM_TR */
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sdram->tr = val & 0x018FC01F;
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break;
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case 0x94: /* SDRAM_ECCCFG */
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sdram->ecccfg = val & 0x00F00000;
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break;
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case 0x98: /* SDRAM_ECCESR */
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val &= 0xFFF0F000;
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if (sdram->eccesr == 0 && val != 0) {
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qemu_irq_raise(sdram->irq);
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} else if (sdram->eccesr != 0 && val == 0) {
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qemu_irq_lower(sdram->irq);
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}
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sdram->eccesr = val;
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break;
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default: /* Error */
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break;
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}
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break;
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}
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}
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static void sdram_reset(void *opaque)
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{
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ppc4xx_sdram_t *sdram;
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sdram = opaque;
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sdram->addr = 0x00000000;
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sdram->bear = 0x00000000;
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sdram->besr0 = 0x00000000; /* No error */
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sdram->besr1 = 0x00000000; /* No error */
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sdram->cfg = 0x00000000;
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sdram->ecccfg = 0x00000000; /* No ECC */
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sdram->eccesr = 0x00000000; /* No error */
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sdram->pmit = 0x07C00000;
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sdram->rtr = 0x05F00000;
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sdram->tr = 0x00854009;
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/* We pre-initialize RAM banks */
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sdram->status = 0x00000000;
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sdram->cfg = 0x00800000;
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}
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void ppc4xx_sdram_init(CPUPPCState *env, qemu_irq irq, int nbanks,
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MemoryRegion *ram_memories,
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hwaddr *ram_bases,
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hwaddr *ram_sizes,
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int do_init)
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{
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ppc4xx_sdram_t *sdram;
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sdram = g_new0(ppc4xx_sdram_t, 1);
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sdram->irq = irq;
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sdram->nbanks = nbanks;
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sdram->ram_memories = ram_memories;
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memset(sdram->ram_bases, 0, 4 * sizeof(hwaddr));
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memcpy(sdram->ram_bases, ram_bases,
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nbanks * sizeof(hwaddr));
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memset(sdram->ram_sizes, 0, 4 * sizeof(hwaddr));
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memcpy(sdram->ram_sizes, ram_sizes,
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nbanks * sizeof(hwaddr));
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qemu_register_reset(&sdram_reset, sdram);
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ppc_dcr_register(env, SDRAM0_CFGADDR,
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sdram, &dcr_read_sdram, &dcr_write_sdram);
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ppc_dcr_register(env, SDRAM0_CFGDATA,
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sdram, &dcr_read_sdram, &dcr_write_sdram);
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if (do_init) {
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sdram_map_bcr(sdram);
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}
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}
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/*
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* Split RAM between SDRAM banks.
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*
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* sdram_bank_sizes[] must be in descending order, that is sizes[i] > sizes[i+1]
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* and must be 0-terminated.
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*
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* The 4xx SDRAM controller supports a small number of banks, and each bank
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* must be one of a small set of sizes. The number of banks and the supported
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* sizes varies by SoC.
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*/
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void ppc4xx_sdram_banks(MemoryRegion *ram, int nr_banks,
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MemoryRegion ram_memories[],
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hwaddr ram_bases[], hwaddr ram_sizes[],
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const ram_addr_t sdram_bank_sizes[])
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{
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ram_addr_t size_left = memory_region_size(ram);
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ram_addr_t base = 0;
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ram_addr_t bank_size;
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int i;
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int j;
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for (i = 0; i < nr_banks; i++) {
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for (j = 0; sdram_bank_sizes[j] != 0; j++) {
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bank_size = sdram_bank_sizes[j];
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if (bank_size <= size_left) {
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char name[32];
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ram_bases[i] = base;
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ram_sizes[i] = bank_size;
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base += bank_size;
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size_left -= bank_size;
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snprintf(name, sizeof(name), "ppc4xx.sdram%d", i);
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memory_region_init_alias(&ram_memories[i], NULL, name, ram,
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ram_bases[i], ram_sizes[i]);
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break;
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}
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}
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if (!size_left) {
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/* No need to use the remaining banks. */
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break;
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}
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}
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if (size_left) {
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ram_addr_t used_size = memory_region_size(ram) - size_left;
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GString *s = g_string_new(NULL);
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for (i = 0; sdram_bank_sizes[i]; i++) {
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g_string_append_printf(s, "%" PRIi64 "%s",
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sdram_bank_sizes[i] / MiB,
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sdram_bank_sizes[i + 1] ? ", " : "");
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}
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error_report("at most %d bank%s of %s MiB each supported",
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nr_banks, nr_banks == 1 ? "" : "s", s->str);
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error_printf("Possible valid RAM size: %" PRIi64 " MiB\n",
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used_size ? used_size / MiB : sdram_bank_sizes[i - 1] / MiB);
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g_string_free(s, true);
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exit(EXIT_FAILURE);
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}
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}
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/*****************************************************************************/
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/* MAL */
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enum {
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MAL0_CFG = 0x180,
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MAL0_ESR = 0x181,
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MAL0_IER = 0x182,
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MAL0_TXCASR = 0x184,
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MAL0_TXCARR = 0x185,
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MAL0_TXEOBISR = 0x186,
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MAL0_TXDEIR = 0x187,
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MAL0_RXCASR = 0x190,
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MAL0_RXCARR = 0x191,
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MAL0_RXEOBISR = 0x192,
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MAL0_RXDEIR = 0x193,
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MAL0_TXCTP0R = 0x1A0,
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MAL0_RXCTP0R = 0x1C0,
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MAL0_RCBS0 = 0x1E0,
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MAL0_RCBS1 = 0x1E1,
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};
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static void ppc4xx_mal_reset(DeviceState *dev)
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{
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Ppc4xxMalState *mal = PPC4xx_MAL(dev);
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mal->cfg = 0x0007C000;
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mal->esr = 0x00000000;
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mal->ier = 0x00000000;
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mal->rxcasr = 0x00000000;
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mal->rxdeir = 0x00000000;
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mal->rxeobisr = 0x00000000;
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mal->txcasr = 0x00000000;
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mal->txdeir = 0x00000000;
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mal->txeobisr = 0x00000000;
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}
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static uint32_t dcr_read_mal(void *opaque, int dcrn)
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{
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Ppc4xxMalState *mal = opaque;
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uint32_t ret;
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switch (dcrn) {
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case MAL0_CFG:
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ret = mal->cfg;
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break;
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case MAL0_ESR:
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ret = mal->esr;
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break;
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case MAL0_IER:
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|
ret = mal->ier;
|
|
break;
|
|
case MAL0_TXCASR:
|
|
ret = mal->txcasr;
|
|
break;
|
|
case MAL0_TXCARR:
|
|
ret = mal->txcarr;
|
|
break;
|
|
case MAL0_TXEOBISR:
|
|
ret = mal->txeobisr;
|
|
break;
|
|
case MAL0_TXDEIR:
|
|
ret = mal->txdeir;
|
|
break;
|
|
case MAL0_RXCASR:
|
|
ret = mal->rxcasr;
|
|
break;
|
|
case MAL0_RXCARR:
|
|
ret = mal->rxcarr;
|
|
break;
|
|
case MAL0_RXEOBISR:
|
|
ret = mal->rxeobisr;
|
|
break;
|
|
case MAL0_RXDEIR:
|
|
ret = mal->rxdeir;
|
|
break;
|
|
default:
|
|
ret = 0;
|
|
break;
|
|
}
|
|
if (dcrn >= MAL0_TXCTP0R && dcrn < MAL0_TXCTP0R + mal->txcnum) {
|
|
ret = mal->txctpr[dcrn - MAL0_TXCTP0R];
|
|
}
|
|
if (dcrn >= MAL0_RXCTP0R && dcrn < MAL0_RXCTP0R + mal->rxcnum) {
|
|
ret = mal->rxctpr[dcrn - MAL0_RXCTP0R];
|
|
}
|
|
if (dcrn >= MAL0_RCBS0 && dcrn < MAL0_RCBS0 + mal->rxcnum) {
|
|
ret = mal->rcbs[dcrn - MAL0_RCBS0];
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static void dcr_write_mal(void *opaque, int dcrn, uint32_t val)
|
|
{
|
|
Ppc4xxMalState *mal = opaque;
|
|
|
|
switch (dcrn) {
|
|
case MAL0_CFG:
|
|
if (val & 0x80000000) {
|
|
ppc4xx_mal_reset(DEVICE(mal));
|
|
}
|
|
mal->cfg = val & 0x00FFC087;
|
|
break;
|
|
case MAL0_ESR:
|
|
/* Read/clear */
|
|
mal->esr &= ~val;
|
|
break;
|
|
case MAL0_IER:
|
|
mal->ier = val & 0x0000001F;
|
|
break;
|
|
case MAL0_TXCASR:
|
|
mal->txcasr = val & 0xF0000000;
|
|
break;
|
|
case MAL0_TXCARR:
|
|
mal->txcarr = val & 0xF0000000;
|
|
break;
|
|
case MAL0_TXEOBISR:
|
|
/* Read/clear */
|
|
mal->txeobisr &= ~val;
|
|
break;
|
|
case MAL0_TXDEIR:
|
|
/* Read/clear */
|
|
mal->txdeir &= ~val;
|
|
break;
|
|
case MAL0_RXCASR:
|
|
mal->rxcasr = val & 0xC0000000;
|
|
break;
|
|
case MAL0_RXCARR:
|
|
mal->rxcarr = val & 0xC0000000;
|
|
break;
|
|
case MAL0_RXEOBISR:
|
|
/* Read/clear */
|
|
mal->rxeobisr &= ~val;
|
|
break;
|
|
case MAL0_RXDEIR:
|
|
/* Read/clear */
|
|
mal->rxdeir &= ~val;
|
|
break;
|
|
}
|
|
if (dcrn >= MAL0_TXCTP0R && dcrn < MAL0_TXCTP0R + mal->txcnum) {
|
|
mal->txctpr[dcrn - MAL0_TXCTP0R] = val;
|
|
}
|
|
if (dcrn >= MAL0_RXCTP0R && dcrn < MAL0_RXCTP0R + mal->rxcnum) {
|
|
mal->rxctpr[dcrn - MAL0_RXCTP0R] = val;
|
|
}
|
|
if (dcrn >= MAL0_RCBS0 && dcrn < MAL0_RCBS0 + mal->rxcnum) {
|
|
mal->rcbs[dcrn - MAL0_RCBS0] = val & 0x000000FF;
|
|
}
|
|
}
|
|
|
|
static void ppc4xx_mal_realize(DeviceState *dev, Error **errp)
|
|
{
|
|
Ppc4xxMalState *mal = PPC4xx_MAL(dev);
|
|
Ppc4xxDcrDeviceState *dcr = PPC4xx_DCR_DEVICE(dev);
|
|
int i;
|
|
|
|
if (mal->txcnum > 32 || mal->rxcnum > 32) {
|
|
error_setg(errp, "invalid TXC/RXC number");
|
|
return;
|
|
}
|
|
|
|
mal->txctpr = g_new0(uint32_t, mal->txcnum);
|
|
mal->rxctpr = g_new0(uint32_t, mal->rxcnum);
|
|
mal->rcbs = g_new0(uint32_t, mal->rxcnum);
|
|
|
|
for (i = 0; i < ARRAY_SIZE(mal->irqs); i++) {
|
|
sysbus_init_irq(SYS_BUS_DEVICE(dev), &mal->irqs[i]);
|
|
}
|
|
|
|
ppc4xx_dcr_register(dcr, MAL0_CFG, mal, &dcr_read_mal, &dcr_write_mal);
|
|
ppc4xx_dcr_register(dcr, MAL0_ESR, mal, &dcr_read_mal, &dcr_write_mal);
|
|
ppc4xx_dcr_register(dcr, MAL0_IER, mal, &dcr_read_mal, &dcr_write_mal);
|
|
ppc4xx_dcr_register(dcr, MAL0_TXCASR, mal, &dcr_read_mal, &dcr_write_mal);
|
|
ppc4xx_dcr_register(dcr, MAL0_TXCARR, mal, &dcr_read_mal, &dcr_write_mal);
|
|
ppc4xx_dcr_register(dcr, MAL0_TXEOBISR, mal, &dcr_read_mal, &dcr_write_mal);
|
|
ppc4xx_dcr_register(dcr, MAL0_TXDEIR, mal, &dcr_read_mal, &dcr_write_mal);
|
|
ppc4xx_dcr_register(dcr, MAL0_RXCASR, mal, &dcr_read_mal, &dcr_write_mal);
|
|
ppc4xx_dcr_register(dcr, MAL0_RXCARR, mal, &dcr_read_mal, &dcr_write_mal);
|
|
ppc4xx_dcr_register(dcr, MAL0_RXEOBISR, mal, &dcr_read_mal, &dcr_write_mal);
|
|
ppc4xx_dcr_register(dcr, MAL0_RXDEIR, mal, &dcr_read_mal, &dcr_write_mal);
|
|
for (i = 0; i < mal->txcnum; i++) {
|
|
ppc4xx_dcr_register(dcr, MAL0_TXCTP0R + i,
|
|
mal, &dcr_read_mal, &dcr_write_mal);
|
|
}
|
|
for (i = 0; i < mal->rxcnum; i++) {
|
|
ppc4xx_dcr_register(dcr, MAL0_RXCTP0R + i,
|
|
mal, &dcr_read_mal, &dcr_write_mal);
|
|
}
|
|
for (i = 0; i < mal->rxcnum; i++) {
|
|
ppc4xx_dcr_register(dcr, MAL0_RCBS0 + i,
|
|
mal, &dcr_read_mal, &dcr_write_mal);
|
|
}
|
|
}
|
|
|
|
static void ppc4xx_mal_finalize(Object *obj)
|
|
{
|
|
Ppc4xxMalState *mal = PPC4xx_MAL(obj);
|
|
|
|
g_free(mal->rcbs);
|
|
g_free(mal->rxctpr);
|
|
g_free(mal->txctpr);
|
|
}
|
|
|
|
static Property ppc4xx_mal_properties[] = {
|
|
DEFINE_PROP_UINT8("txc-num", Ppc4xxMalState, txcnum, 0),
|
|
DEFINE_PROP_UINT8("rxc-num", Ppc4xxMalState, rxcnum, 0),
|
|
DEFINE_PROP_END_OF_LIST(),
|
|
};
|
|
|
|
static void ppc4xx_mal_class_init(ObjectClass *oc, void *data)
|
|
{
|
|
DeviceClass *dc = DEVICE_CLASS(oc);
|
|
|
|
dc->realize = ppc4xx_mal_realize;
|
|
dc->reset = ppc4xx_mal_reset;
|
|
/* Reason: only works as function of a ppc4xx SoC */
|
|
dc->user_creatable = false;
|
|
device_class_set_props(dc, ppc4xx_mal_properties);
|
|
}
|
|
|
|
/*****************************************************************************/
|
|
/* Peripheral local bus arbitrer */
|
|
enum {
|
|
PLB3A0_ACR = 0x077,
|
|
PLB4A0_ACR = 0x081,
|
|
PLB0_BESR = 0x084,
|
|
PLB0_BEAR = 0x086,
|
|
PLB0_ACR = 0x087,
|
|
PLB4A1_ACR = 0x089,
|
|
};
|
|
|
|
static uint32_t dcr_read_plb(void *opaque, int dcrn)
|
|
{
|
|
Ppc4xxPlbState *plb = opaque;
|
|
uint32_t ret;
|
|
|
|
switch (dcrn) {
|
|
case PLB0_ACR:
|
|
ret = plb->acr;
|
|
break;
|
|
case PLB0_BEAR:
|
|
ret = plb->bear;
|
|
break;
|
|
case PLB0_BESR:
|
|
ret = plb->besr;
|
|
break;
|
|
default:
|
|
/* Avoid gcc warning */
|
|
ret = 0;
|
|
break;
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static void dcr_write_plb(void *opaque, int dcrn, uint32_t val)
|
|
{
|
|
Ppc4xxPlbState *plb = opaque;
|
|
|
|
switch (dcrn) {
|
|
case PLB0_ACR:
|
|
/*
|
|
* We don't care about the actual parameters written as
|
|
* we don't manage any priorities on the bus
|
|
*/
|
|
plb->acr = val & 0xF8000000;
|
|
break;
|
|
case PLB0_BEAR:
|
|
/* Read only */
|
|
break;
|
|
case PLB0_BESR:
|
|
/* Write-clear */
|
|
plb->besr &= ~val;
|
|
break;
|
|
}
|
|
}
|
|
|
|
static void ppc405_plb_reset(DeviceState *dev)
|
|
{
|
|
Ppc4xxPlbState *plb = PPC4xx_PLB(dev);
|
|
|
|
plb->acr = 0x00000000;
|
|
plb->bear = 0x00000000;
|
|
plb->besr = 0x00000000;
|
|
}
|
|
|
|
static void ppc405_plb_realize(DeviceState *dev, Error **errp)
|
|
{
|
|
Ppc4xxPlbState *plb = PPC4xx_PLB(dev);
|
|
Ppc4xxDcrDeviceState *dcr = PPC4xx_DCR_DEVICE(dev);
|
|
|
|
ppc4xx_dcr_register(dcr, PLB3A0_ACR, plb, &dcr_read_plb, &dcr_write_plb);
|
|
ppc4xx_dcr_register(dcr, PLB4A0_ACR, plb, &dcr_read_plb, &dcr_write_plb);
|
|
ppc4xx_dcr_register(dcr, PLB0_ACR, plb, &dcr_read_plb, &dcr_write_plb);
|
|
ppc4xx_dcr_register(dcr, PLB0_BEAR, plb, &dcr_read_plb, &dcr_write_plb);
|
|
ppc4xx_dcr_register(dcr, PLB0_BESR, plb, &dcr_read_plb, &dcr_write_plb);
|
|
ppc4xx_dcr_register(dcr, PLB4A1_ACR, plb, &dcr_read_plb, &dcr_write_plb);
|
|
}
|
|
|
|
static void ppc405_plb_class_init(ObjectClass *oc, void *data)
|
|
{
|
|
DeviceClass *dc = DEVICE_CLASS(oc);
|
|
|
|
dc->realize = ppc405_plb_realize;
|
|
dc->reset = ppc405_plb_reset;
|
|
/* Reason: only works as function of a ppc4xx SoC */
|
|
dc->user_creatable = false;
|
|
}
|
|
|
|
/*****************************************************************************/
|
|
/* Peripheral controller */
|
|
enum {
|
|
EBC0_CFGADDR = 0x012,
|
|
EBC0_CFGDATA = 0x013,
|
|
};
|
|
|
|
static uint32_t dcr_read_ebc(void *opaque, int dcrn)
|
|
{
|
|
Ppc4xxEbcState *ebc = opaque;
|
|
uint32_t ret;
|
|
|
|
switch (dcrn) {
|
|
case EBC0_CFGADDR:
|
|
ret = ebc->addr;
|
|
break;
|
|
case EBC0_CFGDATA:
|
|
switch (ebc->addr) {
|
|
case 0x00: /* B0CR */
|
|
ret = ebc->bcr[0];
|
|
break;
|
|
case 0x01: /* B1CR */
|
|
ret = ebc->bcr[1];
|
|
break;
|
|
case 0x02: /* B2CR */
|
|
ret = ebc->bcr[2];
|
|
break;
|
|
case 0x03: /* B3CR */
|
|
ret = ebc->bcr[3];
|
|
break;
|
|
case 0x04: /* B4CR */
|
|
ret = ebc->bcr[4];
|
|
break;
|
|
case 0x05: /* B5CR */
|
|
ret = ebc->bcr[5];
|
|
break;
|
|
case 0x06: /* B6CR */
|
|
ret = ebc->bcr[6];
|
|
break;
|
|
case 0x07: /* B7CR */
|
|
ret = ebc->bcr[7];
|
|
break;
|
|
case 0x10: /* B0AP */
|
|
ret = ebc->bap[0];
|
|
break;
|
|
case 0x11: /* B1AP */
|
|
ret = ebc->bap[1];
|
|
break;
|
|
case 0x12: /* B2AP */
|
|
ret = ebc->bap[2];
|
|
break;
|
|
case 0x13: /* B3AP */
|
|
ret = ebc->bap[3];
|
|
break;
|
|
case 0x14: /* B4AP */
|
|
ret = ebc->bap[4];
|
|
break;
|
|
case 0x15: /* B5AP */
|
|
ret = ebc->bap[5];
|
|
break;
|
|
case 0x16: /* B6AP */
|
|
ret = ebc->bap[6];
|
|
break;
|
|
case 0x17: /* B7AP */
|
|
ret = ebc->bap[7];
|
|
break;
|
|
case 0x20: /* BEAR */
|
|
ret = ebc->bear;
|
|
break;
|
|
case 0x21: /* BESR0 */
|
|
ret = ebc->besr0;
|
|
break;
|
|
case 0x22: /* BESR1 */
|
|
ret = ebc->besr1;
|
|
break;
|
|
case 0x23: /* CFG */
|
|
ret = ebc->cfg;
|
|
break;
|
|
default:
|
|
ret = 0x00000000;
|
|
break;
|
|
}
|
|
break;
|
|
default:
|
|
ret = 0x00000000;
|
|
break;
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static void dcr_write_ebc(void *opaque, int dcrn, uint32_t val)
|
|
{
|
|
Ppc4xxEbcState *ebc = opaque;
|
|
|
|
switch (dcrn) {
|
|
case EBC0_CFGADDR:
|
|
ebc->addr = val;
|
|
break;
|
|
case EBC0_CFGDATA:
|
|
switch (ebc->addr) {
|
|
case 0x00: /* B0CR */
|
|
break;
|
|
case 0x01: /* B1CR */
|
|
break;
|
|
case 0x02: /* B2CR */
|
|
break;
|
|
case 0x03: /* B3CR */
|
|
break;
|
|
case 0x04: /* B4CR */
|
|
break;
|
|
case 0x05: /* B5CR */
|
|
break;
|
|
case 0x06: /* B6CR */
|
|
break;
|
|
case 0x07: /* B7CR */
|
|
break;
|
|
case 0x10: /* B0AP */
|
|
break;
|
|
case 0x11: /* B1AP */
|
|
break;
|
|
case 0x12: /* B2AP */
|
|
break;
|
|
case 0x13: /* B3AP */
|
|
break;
|
|
case 0x14: /* B4AP */
|
|
break;
|
|
case 0x15: /* B5AP */
|
|
break;
|
|
case 0x16: /* B6AP */
|
|
break;
|
|
case 0x17: /* B7AP */
|
|
break;
|
|
case 0x20: /* BEAR */
|
|
break;
|
|
case 0x21: /* BESR0 */
|
|
break;
|
|
case 0x22: /* BESR1 */
|
|
break;
|
|
case 0x23: /* CFG */
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
|
|
static void ppc405_ebc_reset(DeviceState *dev)
|
|
{
|
|
Ppc4xxEbcState *ebc = PPC4xx_EBC(dev);
|
|
int i;
|
|
|
|
ebc->addr = 0x00000000;
|
|
ebc->bap[0] = 0x7F8FFE80;
|
|
ebc->bcr[0] = 0xFFE28000;
|
|
for (i = 0; i < 8; i++) {
|
|
ebc->bap[i] = 0x00000000;
|
|
ebc->bcr[i] = 0x00000000;
|
|
}
|
|
ebc->besr0 = 0x00000000;
|
|
ebc->besr1 = 0x00000000;
|
|
ebc->cfg = 0x80400000;
|
|
}
|
|
|
|
static void ppc405_ebc_realize(DeviceState *dev, Error **errp)
|
|
{
|
|
Ppc4xxEbcState *ebc = PPC4xx_EBC(dev);
|
|
Ppc4xxDcrDeviceState *dcr = PPC4xx_DCR_DEVICE(dev);
|
|
|
|
ppc4xx_dcr_register(dcr, EBC0_CFGADDR, ebc, &dcr_read_ebc, &dcr_write_ebc);
|
|
ppc4xx_dcr_register(dcr, EBC0_CFGDATA, ebc, &dcr_read_ebc, &dcr_write_ebc);
|
|
}
|
|
|
|
static void ppc405_ebc_class_init(ObjectClass *oc, void *data)
|
|
{
|
|
DeviceClass *dc = DEVICE_CLASS(oc);
|
|
|
|
dc->realize = ppc405_ebc_realize;
|
|
dc->reset = ppc405_ebc_reset;
|
|
/* Reason: only works as function of a ppc4xx SoC */
|
|
dc->user_creatable = false;
|
|
}
|
|
|
|
/* PPC4xx_DCR_DEVICE */
|
|
|
|
void ppc4xx_dcr_register(Ppc4xxDcrDeviceState *dev, int dcrn, void *opaque,
|
|
dcr_read_cb dcr_read, dcr_write_cb dcr_write)
|
|
{
|
|
assert(dev->cpu);
|
|
ppc_dcr_register(&dev->cpu->env, dcrn, opaque, dcr_read, dcr_write);
|
|
}
|
|
|
|
bool ppc4xx_dcr_realize(Ppc4xxDcrDeviceState *dev, PowerPCCPU *cpu,
|
|
Error **errp)
|
|
{
|
|
object_property_set_link(OBJECT(dev), "cpu", OBJECT(cpu), &error_abort);
|
|
return sysbus_realize(SYS_BUS_DEVICE(dev), errp);
|
|
}
|
|
|
|
static Property ppc4xx_dcr_properties[] = {
|
|
DEFINE_PROP_LINK("cpu", Ppc4xxDcrDeviceState, cpu, TYPE_POWERPC_CPU,
|
|
PowerPCCPU *),
|
|
DEFINE_PROP_END_OF_LIST(),
|
|
};
|
|
|
|
static void ppc4xx_dcr_class_init(ObjectClass *oc, void *data)
|
|
{
|
|
DeviceClass *dc = DEVICE_CLASS(oc);
|
|
|
|
device_class_set_props(dc, ppc4xx_dcr_properties);
|
|
}
|
|
|
|
static const TypeInfo ppc4xx_types[] = {
|
|
{
|
|
.name = TYPE_PPC4xx_MAL,
|
|
.parent = TYPE_PPC4xx_DCR_DEVICE,
|
|
.instance_size = sizeof(Ppc4xxMalState),
|
|
.instance_finalize = ppc4xx_mal_finalize,
|
|
.class_init = ppc4xx_mal_class_init,
|
|
}, {
|
|
.name = TYPE_PPC4xx_PLB,
|
|
.parent = TYPE_PPC4xx_DCR_DEVICE,
|
|
.instance_size = sizeof(Ppc4xxPlbState),
|
|
.class_init = ppc405_plb_class_init,
|
|
}, {
|
|
.name = TYPE_PPC4xx_EBC,
|
|
.parent = TYPE_PPC4xx_DCR_DEVICE,
|
|
.instance_size = sizeof(Ppc4xxEbcState),
|
|
.class_init = ppc405_ebc_class_init,
|
|
}, {
|
|
.name = TYPE_PPC4xx_DCR_DEVICE,
|
|
.parent = TYPE_SYS_BUS_DEVICE,
|
|
.instance_size = sizeof(Ppc4xxDcrDeviceState),
|
|
.class_init = ppc4xx_dcr_class_init,
|
|
.abstract = true,
|
|
}
|
|
};
|
|
|
|
DEFINE_TYPES(ppc4xx_types)
|