777aca2fd3
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@549 c046a42c-6fe2-441c-8c8c-71466251a162
387 lines
11 KiB
C
387 lines
11 KiB
C
/*
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* i386 helpers (without register variable usage)
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*
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* Copyright (c) 2003 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <stdarg.h>
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#include <stdlib.h>
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#include <stdio.h>
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#include <string.h>
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#include <inttypes.h>
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#include <signal.h>
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#include <assert.h>
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#include <sys/mman.h>
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#include "cpu.h"
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#include "exec-all.h"
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//#define DEBUG_MMU
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CPUX86State *cpu_x86_init(void)
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{
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CPUX86State *env;
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int i;
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static int inited;
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cpu_exec_init();
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env = malloc(sizeof(CPUX86State));
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if (!env)
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return NULL;
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memset(env, 0, sizeof(CPUX86State));
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/* basic FPU init */
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for(i = 0;i < 8; i++)
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env->fptags[i] = 1;
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env->fpuc = 0x37f;
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/* flags setup : we activate the IRQs by default as in user mode */
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env->eflags = 0x2 | IF_MASK;
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tlb_flush(env);
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#ifdef CONFIG_SOFTMMU
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env->hflags |= HF_SOFTMMU_MASK;
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#endif
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/* init various static tables */
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if (!inited) {
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inited = 1;
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optimize_flags_init();
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}
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return env;
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}
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void cpu_x86_close(CPUX86State *env)
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{
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free(env);
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}
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/***********************************************************/
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/* x86 debug */
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static const char *cc_op_str[] = {
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"DYNAMIC",
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"EFLAGS",
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"MULB",
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"MULW",
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"MULL",
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"ADDB",
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"ADDW",
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"ADDL",
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"ADCB",
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"ADCW",
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"ADCL",
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"SUBB",
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"SUBW",
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"SUBL",
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"SBBB",
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"SBBW",
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"SBBL",
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"LOGICB",
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"LOGICW",
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"LOGICL",
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"INCB",
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"INCW",
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"INCL",
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"DECB",
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"DECW",
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"DECL",
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"SHLB",
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"SHLW",
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"SHLL",
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"SARB",
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"SARW",
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"SARL",
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};
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void cpu_x86_dump_state(CPUX86State *env, FILE *f, int flags)
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{
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int eflags, i;
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char cc_op_name[32];
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static const char *seg_name[6] = { "ES", "CS", "SS", "DS", "FS", "GS" };
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eflags = env->eflags;
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fprintf(f, "EAX=%08x EBX=%08x ECX=%08x EDX=%08x\n"
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"ESI=%08x EDI=%08x EBP=%08x ESP=%08x\n"
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"EIP=%08x EFL=%08x [%c%c%c%c%c%c%c] CPL=%d II=%d\n",
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env->regs[R_EAX], env->regs[R_EBX], env->regs[R_ECX], env->regs[R_EDX],
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env->regs[R_ESI], env->regs[R_EDI], env->regs[R_EBP], env->regs[R_ESP],
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env->eip, eflags,
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eflags & DF_MASK ? 'D' : '-',
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eflags & CC_O ? 'O' : '-',
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eflags & CC_S ? 'S' : '-',
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eflags & CC_Z ? 'Z' : '-',
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eflags & CC_A ? 'A' : '-',
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eflags & CC_P ? 'P' : '-',
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eflags & CC_C ? 'C' : '-',
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env->hflags & HF_CPL_MASK,
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(env->hflags >> HF_INHIBIT_IRQ_SHIFT) & 1);
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for(i = 0; i < 6; i++) {
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SegmentCache *sc = &env->segs[i];
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fprintf(f, "%s =%04x %08x %08x %08x\n",
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seg_name[i],
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sc->selector,
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(int)sc->base,
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sc->limit,
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sc->flags);
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}
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fprintf(f, "LDT=%04x %08x %08x %08x\n",
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env->ldt.selector,
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(int)env->ldt.base,
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env->ldt.limit,
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env->ldt.flags);
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fprintf(f, "TR =%04x %08x %08x %08x\n",
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env->tr.selector,
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(int)env->tr.base,
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env->tr.limit,
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env->tr.flags);
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fprintf(f, "GDT= %08x %08x\n",
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(int)env->gdt.base, env->gdt.limit);
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fprintf(f, "IDT= %08x %08x\n",
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(int)env->idt.base, env->idt.limit);
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fprintf(f, "CR0=%08x CR2=%08x CR3=%08x CR4=%08x\n",
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env->cr[0], env->cr[2], env->cr[3], env->cr[4]);
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if (flags & X86_DUMP_CCOP) {
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if ((unsigned)env->cc_op < CC_OP_NB)
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strcpy(cc_op_name, cc_op_str[env->cc_op]);
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else
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snprintf(cc_op_name, sizeof(cc_op_name), "[%d]", env->cc_op);
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fprintf(f, "CCS=%08x CCD=%08x CCO=%-8s\n",
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env->cc_src, env->cc_dst, cc_op_name);
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}
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if (flags & X86_DUMP_FPU) {
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fprintf(f, "ST0=%f ST1=%f ST2=%f ST3=%f\n",
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(double)env->fpregs[0],
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(double)env->fpregs[1],
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(double)env->fpregs[2],
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(double)env->fpregs[3]);
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fprintf(f, "ST4=%f ST5=%f ST6=%f ST7=%f\n",
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(double)env->fpregs[4],
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(double)env->fpregs[5],
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(double)env->fpregs[7],
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(double)env->fpregs[8]);
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}
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}
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/***********************************************************/
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/* x86 mmu */
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/* XXX: add PGE support */
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/* called when cr3 or PG bit are modified */
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static int last_pg_state = -1;
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static uint32_t a20_mask;
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int a20_enabled;
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void cpu_x86_set_a20(CPUX86State *env, int a20_state)
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{
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a20_state = (a20_state != 0);
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if (a20_state != a20_enabled) {
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#if defined(DEBUG_MMU)
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printf("A20 update: a20=%d\n", a20_state);
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#endif
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/* if the cpu is currently executing code, we must unlink it and
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all the potentially executing TB */
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cpu_interrupt(env, 0);
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/* when a20 is changed, all the MMU mappings are invalid, so
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we must flush everything */
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tlb_flush(env);
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a20_enabled = a20_state;
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if (a20_enabled)
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a20_mask = 0xffffffff;
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else
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a20_mask = 0xffefffff;
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}
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}
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void cpu_x86_update_cr0(CPUX86State *env)
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{
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int pg_state, pe_state;
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#if defined(DEBUG_MMU)
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printf("CR0 update: CR0=0x%08x\n", env->cr[0]);
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#endif
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pg_state = env->cr[0] & CR0_PG_MASK;
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if (pg_state != last_pg_state) {
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tlb_flush(env);
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last_pg_state = pg_state;
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}
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/* update PE flag in hidden flags */
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pe_state = (env->cr[0] & CR0_PE_MASK);
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env->hflags = (env->hflags & ~HF_PE_MASK) | (pe_state << HF_PE_SHIFT);
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/* ensure that ADDSEG is always set in real mode */
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env->hflags |= ((pe_state ^ 1) << HF_ADDSEG_SHIFT);
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}
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void cpu_x86_update_cr3(CPUX86State *env)
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{
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if (env->cr[0] & CR0_PG_MASK) {
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#if defined(DEBUG_MMU)
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printf("CR3 update: CR3=%08x\n", env->cr[3]);
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#endif
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tlb_flush(env);
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}
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}
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void cpu_x86_init_mmu(CPUX86State *env)
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{
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a20_enabled = 1;
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a20_mask = 0xffffffff;
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last_pg_state = -1;
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cpu_x86_update_cr0(env);
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}
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/* XXX: also flush 4MB pages */
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void cpu_x86_flush_tlb(CPUX86State *env, uint32_t addr)
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{
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tlb_flush_page(env, addr);
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}
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/* return value:
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-1 = cannot handle fault
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0 = nothing more to do
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1 = generate PF fault
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2 = soft MMU activation required for this block
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*/
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int cpu_x86_handle_mmu_fault(CPUX86State *env, uint32_t addr,
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int is_write, int is_user, int is_softmmu)
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{
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uint8_t *pde_ptr, *pte_ptr;
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uint32_t pde, pte, virt_addr;
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int error_code, is_dirty, prot, page_size, ret;
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unsigned long paddr, vaddr, page_offset;
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#if defined(DEBUG_MMU)
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printf("MMU fault: addr=0x%08x w=%d u=%d eip=%08x\n",
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addr, is_write, is_user, env->eip);
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#endif
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if (env->user_mode_only) {
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/* user mode only emulation */
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error_code = 0;
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goto do_fault;
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}
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if (!(env->cr[0] & CR0_PG_MASK)) {
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pte = addr;
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virt_addr = addr & TARGET_PAGE_MASK;
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prot = PROT_READ | PROT_WRITE;
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page_size = 4096;
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goto do_mapping;
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}
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/* page directory entry */
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pde_ptr = phys_ram_base +
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(((env->cr[3] & ~0xfff) + ((addr >> 20) & ~3)) & a20_mask);
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pde = ldl_raw(pde_ptr);
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if (!(pde & PG_PRESENT_MASK)) {
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error_code = 0;
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goto do_fault;
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}
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if (is_user) {
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if (!(pde & PG_USER_MASK))
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goto do_fault_protect;
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if (is_write && !(pde & PG_RW_MASK))
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goto do_fault_protect;
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} else {
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if ((env->cr[0] & CR0_WP_MASK) && (pde & PG_USER_MASK) &&
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is_write && !(pde & PG_RW_MASK))
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goto do_fault_protect;
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}
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/* if PSE bit is set, then we use a 4MB page */
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if ((pde & PG_PSE_MASK) && (env->cr[4] & CR4_PSE_MASK)) {
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is_dirty = is_write && !(pde & PG_DIRTY_MASK);
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if (!(pde & PG_ACCESSED_MASK) || is_dirty) {
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pde |= PG_ACCESSED_MASK;
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if (is_dirty)
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pde |= PG_DIRTY_MASK;
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stl_raw(pde_ptr, pde);
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}
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pte = pde & ~0x003ff000; /* align to 4MB */
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page_size = 4096 * 1024;
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virt_addr = addr & ~0x003fffff;
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} else {
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if (!(pde & PG_ACCESSED_MASK)) {
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pde |= PG_ACCESSED_MASK;
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stl_raw(pde_ptr, pde);
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}
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/* page directory entry */
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pte_ptr = phys_ram_base +
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(((pde & ~0xfff) + ((addr >> 10) & 0xffc)) & a20_mask);
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pte = ldl_raw(pte_ptr);
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if (!(pte & PG_PRESENT_MASK)) {
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error_code = 0;
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goto do_fault;
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}
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if (is_user) {
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if (!(pte & PG_USER_MASK))
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goto do_fault_protect;
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if (is_write && !(pte & PG_RW_MASK))
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goto do_fault_protect;
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} else {
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if ((env->cr[0] & CR0_WP_MASK) && (pte & PG_USER_MASK) &&
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is_write && !(pte & PG_RW_MASK))
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goto do_fault_protect;
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}
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is_dirty = is_write && !(pte & PG_DIRTY_MASK);
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if (!(pte & PG_ACCESSED_MASK) || is_dirty) {
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pte |= PG_ACCESSED_MASK;
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if (is_dirty)
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pte |= PG_DIRTY_MASK;
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stl_raw(pte_ptr, pte);
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}
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page_size = 4096;
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virt_addr = addr & ~0xfff;
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}
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/* the page can be put in the TLB */
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prot = PROT_READ;
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if (pte & PG_DIRTY_MASK) {
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/* only set write access if already dirty... otherwise wait
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for dirty access */
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if (is_user) {
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if (pte & PG_RW_MASK)
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prot |= PROT_WRITE;
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} else {
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if (!(env->cr[0] & CR0_WP_MASK) || !(pte & PG_USER_MASK) ||
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(pte & PG_RW_MASK))
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prot |= PROT_WRITE;
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}
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}
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do_mapping:
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pte = pte & a20_mask;
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/* Even if 4MB pages, we map only one 4KB page in the cache to
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avoid filling it too fast */
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page_offset = (addr & TARGET_PAGE_MASK) & (page_size - 1);
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paddr = (pte & TARGET_PAGE_MASK) + page_offset;
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vaddr = virt_addr + page_offset;
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ret = tlb_set_page(env, vaddr, paddr, prot, is_user, is_softmmu);
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return ret;
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do_fault_protect:
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error_code = PG_ERROR_P_MASK;
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do_fault:
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env->cr[2] = addr;
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env->error_code = (is_write << PG_ERROR_W_BIT) | error_code;
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if (is_user)
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env->error_code |= PG_ERROR_U_MASK;
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return 1;
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}
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