005e1a0a02
Add uses of the float32/float64 boxing and unboxing macros so that the ARM linux-user targets will compile with USE_SOFTFLOAT_STRUCT_TYPES enabled. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
113 lines
3.5 KiB
C
113 lines
3.5 KiB
C
/*
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NetWinder Floating Point Emulator
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(c) Rebel.COM, 1998,1999
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Direct questions, comments to Scott Bambrough <scottb@netwinder.org>
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "fpa11.h"
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#include "softfloat.h"
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#include "fpopcode.h"
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#include "fpsr.h"
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//#include "fpmodule.h"
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//#include "fpmodule.inl"
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const floatx80 floatx80Constant[] = {
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{ 0x0000000000000000ULL, 0x0000}, /* extended 0.0 */
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{ 0x8000000000000000ULL, 0x3fff}, /* extended 1.0 */
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{ 0x8000000000000000ULL, 0x4000}, /* extended 2.0 */
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{ 0xc000000000000000ULL, 0x4000}, /* extended 3.0 */
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{ 0x8000000000000000ULL, 0x4001}, /* extended 4.0 */
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{ 0xa000000000000000ULL, 0x4001}, /* extended 5.0 */
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{ 0x8000000000000000ULL, 0x3ffe}, /* extended 0.5 */
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{ 0xa000000000000000ULL, 0x4002} /* extended 10.0 */
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};
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const float64 float64Constant[] = {
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const_float64(0x0000000000000000ULL), /* double 0.0 */
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const_float64(0x3ff0000000000000ULL), /* double 1.0 */
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const_float64(0x4000000000000000ULL), /* double 2.0 */
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const_float64(0x4008000000000000ULL), /* double 3.0 */
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const_float64(0x4010000000000000ULL), /* double 4.0 */
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const_float64(0x4014000000000000ULL), /* double 5.0 */
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const_float64(0x3fe0000000000000ULL), /* double 0.5 */
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const_float64(0x4024000000000000ULL) /* double 10.0 */
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};
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const float32 float32Constant[] = {
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const_float32(0x00000000), /* single 0.0 */
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const_float32(0x3f800000), /* single 1.0 */
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const_float32(0x40000000), /* single 2.0 */
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const_float32(0x40400000), /* single 3.0 */
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const_float32(0x40800000), /* single 4.0 */
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const_float32(0x40a00000), /* single 5.0 */
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const_float32(0x3f000000), /* single 0.5 */
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const_float32(0x41200000) /* single 10.0 */
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};
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unsigned int getRegisterCount(const unsigned int opcode)
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{
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unsigned int nRc;
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switch (opcode & MASK_REGISTER_COUNT)
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{
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case 0x00000000: nRc = 4; break;
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case 0x00008000: nRc = 1; break;
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case 0x00400000: nRc = 2; break;
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case 0x00408000: nRc = 3; break;
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default: nRc = 0;
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}
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return(nRc);
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}
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unsigned int getDestinationSize(const unsigned int opcode)
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{
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unsigned int nRc;
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switch (opcode & MASK_DESTINATION_SIZE)
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{
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case 0x00000000: nRc = typeSingle; break;
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case 0x00000080: nRc = typeDouble; break;
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case 0x00080000: nRc = typeExtended; break;
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default: nRc = typeNone;
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}
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return(nRc);
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}
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/* condition code lookup table
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index into the table is test code: EQ, NE, ... LT, GT, AL, NV
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bit position in short is condition code: NZCV */
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static const unsigned short aCC[16] = {
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0xF0F0, // EQ == Z set
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0x0F0F, // NE
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0xCCCC, // CS == C set
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0x3333, // CC
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0xFF00, // MI == N set
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0x00FF, // PL
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0xAAAA, // VS == V set
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0x5555, // VC
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0x0C0C, // HI == C set && Z clear
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0xF3F3, // LS == C clear || Z set
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0xAA55, // GE == (N==V)
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0x55AA, // LT == (N!=V)
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0x0A05, // GT == (!Z && (N==V))
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0xF5FA, // LE == (Z || (N!=V))
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0xFFFF, // AL always
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0 // NV
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};
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