e38d3c5ce5
$ ./scripts/codeconverter/converter.py -i \ --pattern=TypeCheckMacro $(git grep -l '' -- '*.[ch]') Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Message-Id: <20200831210740.126168-12-ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
80 lines
2.2 KiB
C
80 lines
2.2 KiB
C
/*
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* SiFive UART interface
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*
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* Copyright (c) 2016 Stefan O'Rear
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* Copyright (c) 2017 SiFive, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef HW_SIFIVE_UART_H
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#define HW_SIFIVE_UART_H
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#include "chardev/char-fe.h"
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#include "hw/sysbus.h"
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#include "qom/object.h"
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enum {
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SIFIVE_UART_TXFIFO = 0,
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SIFIVE_UART_RXFIFO = 4,
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SIFIVE_UART_TXCTRL = 8,
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SIFIVE_UART_TXMARK = 10,
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SIFIVE_UART_RXCTRL = 12,
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SIFIVE_UART_RXMARK = 14,
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SIFIVE_UART_IE = 16,
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SIFIVE_UART_IP = 20,
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SIFIVE_UART_DIV = 24,
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SIFIVE_UART_MAX = 32
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};
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enum {
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SIFIVE_UART_IE_TXWM = 1, /* Transmit watermark interrupt enable */
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SIFIVE_UART_IE_RXWM = 2 /* Receive watermark interrupt enable */
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};
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enum {
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SIFIVE_UART_IP_TXWM = 1, /* Transmit watermark interrupt pending */
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SIFIVE_UART_IP_RXWM = 2 /* Receive watermark interrupt pending */
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};
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#define SIFIVE_UART_GET_TXCNT(txctrl) ((txctrl >> 16) & 0x7)
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#define SIFIVE_UART_GET_RXCNT(rxctrl) ((rxctrl >> 16) & 0x7)
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#define TYPE_SIFIVE_UART "riscv.sifive.uart"
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typedef struct SiFiveUARTState SiFiveUARTState;
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DECLARE_INSTANCE_CHECKER(SiFiveUARTState, SIFIVE_UART,
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TYPE_SIFIVE_UART)
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struct SiFiveUARTState {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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qemu_irq irq;
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MemoryRegion mmio;
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CharBackend chr;
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uint8_t rx_fifo[8];
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unsigned int rx_fifo_len;
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uint32_t ie;
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uint32_t ip;
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uint32_t txctrl;
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uint32_t rxctrl;
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uint32_t div;
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};
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SiFiveUARTState *sifive_uart_create(MemoryRegion *address_space, hwaddr base,
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Chardev *chr, qemu_irq irq);
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#endif
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