0ee20e6658
An IDE bus provided by AHCI can only take a single IDE drive. If you add a drive as slave, qemu used to accept the command line but the device wouldn't be actually usable. Catch the situation instead and error out. Signed-off-by: Kevin Wolf <kwolf@redhat.com>
242 lines
7.1 KiB
C
242 lines
7.1 KiB
C
/*
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* QEMU IDE Emulation: PCI VIA82C686B support.
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*
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* Copyright (c) 2003 Fabrice Bellard
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* Copyright (c) 2006 Openedhand Ltd.
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* Copyright (c) 2010 Huacai Chen <zltjiangshi@gmail.com>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include <hw/hw.h>
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#include <hw/i386/pc.h>
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#include <hw/pci/pci.h>
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#include <hw/isa/isa.h>
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#include "block/block.h"
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#include "sysemu/sysemu.h"
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#include "sysemu/dma.h"
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#include <hw/ide/pci.h>
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static uint64_t bmdma_read(void *opaque, hwaddr addr,
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unsigned size)
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{
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BMDMAState *bm = opaque;
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uint32_t val;
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if (size != 1) {
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return ((uint64_t)1 << (size * 8)) - 1;
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}
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switch (addr & 3) {
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case 0:
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val = bm->cmd;
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break;
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case 2:
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val = bm->status;
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break;
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default:
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val = 0xff;
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break;
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}
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#ifdef DEBUG_IDE
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printf("bmdma: readb 0x%02x : 0x%02x\n", addr, val);
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#endif
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return val;
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}
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static void bmdma_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned size)
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{
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BMDMAState *bm = opaque;
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if (size != 1) {
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return;
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}
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#ifdef DEBUG_IDE
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printf("bmdma: writeb 0x%02x : 0x%02x\n", addr, val);
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#endif
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switch (addr & 3) {
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case 0:
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bmdma_cmd_writeb(bm, val);
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break;
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case 2:
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bm->status = (val & 0x60) | (bm->status & 1) | (bm->status & ~val & 0x06);
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break;
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default:;
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}
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}
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static const MemoryRegionOps via_bmdma_ops = {
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.read = bmdma_read,
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.write = bmdma_write,
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};
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static void bmdma_setup_bar(PCIIDEState *d)
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{
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int i;
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memory_region_init(&d->bmdma_bar, "via-bmdma-container", 16);
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for(i = 0;i < 2; i++) {
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BMDMAState *bm = &d->bmdma[i];
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memory_region_init_io(&bm->extra_io, &via_bmdma_ops, bm,
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"via-bmdma", 4);
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memory_region_add_subregion(&d->bmdma_bar, i * 8, &bm->extra_io);
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memory_region_init_io(&bm->addr_ioport, &bmdma_addr_ioport_ops, bm,
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"bmdma", 4);
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memory_region_add_subregion(&d->bmdma_bar, i * 8 + 4, &bm->addr_ioport);
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}
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}
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static void via_reset(void *opaque)
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{
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PCIIDEState *d = opaque;
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uint8_t *pci_conf = d->dev.config;
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int i;
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for (i = 0; i < 2; i++) {
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ide_bus_reset(&d->bus[i]);
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}
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pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_WAIT);
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pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_FAST_BACK |
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PCI_STATUS_DEVSEL_MEDIUM);
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pci_set_long(pci_conf + PCI_BASE_ADDRESS_0, 0x000001f0);
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pci_set_long(pci_conf + PCI_BASE_ADDRESS_1, 0x000003f4);
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pci_set_long(pci_conf + PCI_BASE_ADDRESS_2, 0x00000170);
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pci_set_long(pci_conf + PCI_BASE_ADDRESS_3, 0x00000374);
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pci_set_long(pci_conf + PCI_BASE_ADDRESS_4, 0x0000cc01); /* BMIBA: 20-23h */
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pci_set_long(pci_conf + PCI_INTERRUPT_LINE, 0x0000010e);
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/* IDE chip enable, IDE configuration 1/2, IDE FIFO Configuration*/
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pci_set_long(pci_conf + 0x40, 0x0a090600);
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/* IDE misc configuration 1/2/3 */
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pci_set_long(pci_conf + 0x44, 0x00c00068);
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/* IDE Timing control */
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pci_set_long(pci_conf + 0x48, 0xa8a8a8a8);
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/* IDE Address Setup Time */
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pci_set_long(pci_conf + 0x4c, 0x000000ff);
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/* UltraDMA Extended Timing Control*/
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pci_set_long(pci_conf + 0x50, 0x07070707);
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/* UltraDMA FIFO Control */
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pci_set_long(pci_conf + 0x54, 0x00000004);
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/* IDE primary sector size */
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pci_set_long(pci_conf + 0x60, 0x00000200);
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/* IDE secondary sector size */
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pci_set_long(pci_conf + 0x68, 0x00000200);
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/* PCI PM Block */
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pci_set_long(pci_conf + 0xc0, 0x00020001);
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}
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static void vt82c686b_init_ports(PCIIDEState *d) {
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static const struct {
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int iobase;
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int iobase2;
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int isairq;
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} port_info[] = {
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{0x1f0, 0x3f6, 14},
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{0x170, 0x376, 15},
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};
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int i;
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for (i = 0; i < 2; i++) {
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ide_bus_new(&d->bus[i], &d->dev.qdev, i, 2);
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ide_init_ioport(&d->bus[i], NULL, port_info[i].iobase,
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port_info[i].iobase2);
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ide_init2(&d->bus[i], isa_get_irq(NULL, port_info[i].isairq));
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bmdma_init(&d->bus[i], &d->bmdma[i], d);
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d->bmdma[i].bus = &d->bus[i];
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qemu_add_vm_change_state_handler(d->bus[i].dma->ops->restart_cb,
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&d->bmdma[i].dma);
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}
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}
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/* via ide func */
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static int vt82c686b_ide_initfn(PCIDevice *dev)
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{
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PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, dev);
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uint8_t *pci_conf = d->dev.config;
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pci_config_set_prog_interface(pci_conf, 0x8a); /* legacy ATA mode */
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pci_set_long(pci_conf + PCI_CAPABILITY_LIST, 0x000000c0);
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qemu_register_reset(via_reset, d);
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bmdma_setup_bar(d);
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pci_register_bar(&d->dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &d->bmdma_bar);
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vmstate_register(&dev->qdev, 0, &vmstate_ide_pci, d);
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vt82c686b_init_ports(d);
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return 0;
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}
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static void vt82c686b_ide_exitfn(PCIDevice *dev)
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{
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PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, dev);
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unsigned i;
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for (i = 0; i < 2; ++i) {
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memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].extra_io);
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memory_region_destroy(&d->bmdma[i].extra_io);
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memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].addr_ioport);
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memory_region_destroy(&d->bmdma[i].addr_ioport);
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}
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memory_region_destroy(&d->bmdma_bar);
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}
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void vt82c686b_ide_init(PCIBus *bus, DriveInfo **hd_table, int devfn)
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{
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PCIDevice *dev;
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dev = pci_create_simple(bus, devfn, "via-ide");
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pci_ide_create_devs(dev, hd_table);
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}
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static void via_ide_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
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k->init = vt82c686b_ide_initfn;
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k->exit = vt82c686b_ide_exitfn;
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k->vendor_id = PCI_VENDOR_ID_VIA;
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k->device_id = PCI_DEVICE_ID_VIA_IDE;
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k->revision = 0x06;
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k->class_id = PCI_CLASS_STORAGE_IDE;
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dc->no_user = 1;
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}
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static const TypeInfo via_ide_info = {
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.name = "via-ide",
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.parent = TYPE_PCI_DEVICE,
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.instance_size = sizeof(PCIIDEState),
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.class_init = via_ide_class_init,
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};
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static void via_ide_register_types(void)
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{
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type_register_static(&via_ide_info);
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}
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type_init(via_ide_register_types)
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