300 lines
9.5 KiB
C
300 lines
9.5 KiB
C
/*
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* Toshiba TC6393XB I/O Controller.
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* Found in Sharp Zaurus SL-6000 (tosa) or some
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* Toshiba e-Series PDAs.
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*
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* Most features are currently unsupported!!!
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*
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* This code is licensed under the GNU GPL v2.
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*/
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#include "hw.h"
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#include "pxa.h"
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#include "devices.h"
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#define TC6393XB_GPIOS 16
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#define SCR_REVID 0x08 /* b Revision ID */
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#define SCR_ISR 0x50 /* b Interrupt Status */
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#define SCR_IMR 0x52 /* b Interrupt Mask */
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#define SCR_IRR 0x54 /* b Interrupt Routing */
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#define SCR_GPER 0x60 /* w GP Enable */
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#define SCR_GPI_SR(i) (0x64 + (i)) /* b3 GPI Status */
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#define SCR_GPI_IMR(i) (0x68 + (i)) /* b3 GPI INT Mask */
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#define SCR_GPI_EDER(i) (0x6c + (i)) /* b3 GPI Edge Detect Enable */
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#define SCR_GPI_LIR(i) (0x70 + (i)) /* b3 GPI Level Invert */
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#define SCR_GPO_DSR(i) (0x78 + (i)) /* b3 GPO Data Set */
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#define SCR_GPO_DOECR(i) (0x7c + (i)) /* b3 GPO Data OE Control */
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#define SCR_GP_IARCR(i) (0x80 + (i)) /* b3 GP Internal Active Register Control */
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#define SCR_GP_IARLCR(i) (0x84 + (i)) /* b3 GP INTERNAL Active Register Level Control */
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#define SCR_GPI_BCR(i) (0x88 + (i)) /* b3 GPI Buffer Control */
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#define SCR_GPA_IARCR 0x8c /* w GPa Internal Active Register Control */
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#define SCR_GPA_IARLCR 0x90 /* w GPa Internal Active Register Level Control */
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#define SCR_GPA_BCR 0x94 /* w GPa Buffer Control */
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#define SCR_CCR 0x98 /* w Clock Control */
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#define SCR_PLL2CR 0x9a /* w PLL2 Control */
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#define SCR_PLL1CR 0x9c /* l PLL1 Control */
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#define SCR_DIARCR 0xa0 /* b Device Internal Active Register Control */
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#define SCR_DBOCR 0xa1 /* b Device Buffer Off Control */
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#define SCR_FER 0xe0 /* b Function Enable */
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#define SCR_MCR 0xe4 /* w Mode Control */
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#define SCR_CONFIG 0xfc /* b Configuration Control */
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#define SCR_DEBUG 0xff /* b Debug */
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struct tc6393xb_s {
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target_phys_addr_t target_base;
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struct {
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uint8_t ISR;
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uint8_t IMR;
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uint8_t IRR;
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uint16_t GPER;
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uint8_t GPI_SR[3];
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uint8_t GPI_IMR[3];
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uint8_t GPI_EDER[3];
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uint8_t GPI_LIR[3];
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uint8_t GP_IARCR[3];
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uint8_t GP_IARLCR[3];
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uint8_t GPI_BCR[3];
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uint16_t GPA_IARCR;
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uint16_t GPA_IARLCR;
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uint16_t CCR;
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uint16_t PLL2CR;
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uint32_t PLL1CR;
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uint8_t DIARCR;
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uint8_t DBOCR;
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uint8_t FER;
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uint16_t MCR;
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uint8_t CONFIG;
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uint8_t DEBUG;
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} scr;
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uint32_t gpio_dir;
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uint32_t gpio_level;
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uint32_t prev_level;
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qemu_irq handler[TC6393XB_GPIOS];
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qemu_irq *gpio_in;
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};
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qemu_irq *tc6393xb_gpio_in_get(struct tc6393xb_s *s)
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{
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return s->gpio_in;
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}
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static void tc6393xb_gpio_set(void *opaque, int line, int level)
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{
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// struct tc6393xb_s *s = opaque;
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if (line > TC6393XB_GPIOS) {
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printf("%s: No GPIO pin %i\n", __FUNCTION__, line);
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return;
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}
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// FIXME: how does the chip reflect the GPIO input level change?
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}
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void tc6393xb_gpio_out_set(struct tc6393xb_s *s, int line,
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qemu_irq handler)
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{
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if (line >= TC6393XB_GPIOS) {
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fprintf(stderr, "TC6393xb: no GPIO pin %d\n", line);
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return;
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}
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s->handler[line] = handler;
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}
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static void tc6393xb_gpio_handler_update(struct tc6393xb_s *s)
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{
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uint32_t level, diff;
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int bit;
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level = s->gpio_level & s->gpio_dir;
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for (diff = s->prev_level ^ level; diff; diff ^= 1 << bit) {
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bit = ffs(diff) - 1;
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qemu_set_irq(s->handler[bit], (level >> bit) & 1);
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}
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s->prev_level = level;
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}
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#define SCR_REG_B(N) \
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case SCR_ ##N: return s->scr.N
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#define SCR_REG_W(N) \
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case SCR_ ##N: return s->scr.N; \
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case SCR_ ##N + 1: return s->scr.N >> 8;
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#define SCR_REG_L(N) \
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case SCR_ ##N: return s->scr.N; \
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case SCR_ ##N + 1: return s->scr.N >> 8; \
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case SCR_ ##N + 2: return s->scr.N >> 16; \
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case SCR_ ##N + 3: return s->scr.N >> 24;
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#define SCR_REG_A(N) \
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case SCR_ ##N(0): return s->scr.N[0]; \
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case SCR_ ##N(1): return s->scr.N[1]; \
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case SCR_ ##N(2): return s->scr.N[2]
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static uint32_t tc6393xb_readb(void *opaque, target_phys_addr_t addr)
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{
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struct tc6393xb_s *s = opaque;
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addr -= s->target_base;
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switch (addr) {
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case SCR_REVID:
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return 3;
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case SCR_REVID+1:
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return 0;
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SCR_REG_B(ISR);
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SCR_REG_B(IMR);
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SCR_REG_B(IRR);
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SCR_REG_W(GPER);
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SCR_REG_A(GPI_SR);
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SCR_REG_A(GPI_IMR);
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SCR_REG_A(GPI_EDER);
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SCR_REG_A(GPI_LIR);
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case SCR_GPO_DSR(0):
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case SCR_GPO_DSR(1):
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case SCR_GPO_DSR(2):
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return (s->gpio_level >> ((addr - SCR_GPO_DSR(0)) * 8)) & 0xff;
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case SCR_GPO_DOECR(0):
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case SCR_GPO_DOECR(1):
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case SCR_GPO_DOECR(2):
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return (s->gpio_dir >> ((addr - SCR_GPO_DOECR(0)) * 8)) & 0xff;
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SCR_REG_A(GP_IARCR);
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SCR_REG_A(GP_IARLCR);
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SCR_REG_A(GPI_BCR);
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SCR_REG_W(GPA_IARCR);
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SCR_REG_W(GPA_IARLCR);
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SCR_REG_W(CCR);
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SCR_REG_W(PLL2CR);
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SCR_REG_L(PLL1CR);
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SCR_REG_B(DIARCR);
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SCR_REG_B(DBOCR);
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SCR_REG_B(FER);
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SCR_REG_W(MCR);
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SCR_REG_B(CONFIG);
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SCR_REG_B(DEBUG);
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}
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fprintf(stderr, "tc6393xb: unhandled read at %08x\n", (uint32_t) addr);
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return 0;
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}
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#undef SCR_REG_B
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#undef SCR_REG_W
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#undef SCR_REG_L
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#undef SCR_REG_A
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#define SCR_REG_B(N) \
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case SCR_ ##N: s->scr.N = value; break;
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#define SCR_REG_W(N) \
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case SCR_ ##N: s->scr.N = (s->scr.N & ~0xff) | (value & 0xff); break; \
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case SCR_ ##N + 1: s->scr.N = (s->scr.N & 0xff) | (value << 8); break
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#define SCR_REG_L(N) \
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case SCR_ ##N: s->scr.N = (s->scr.N & ~0xff) | (value & 0xff); break; \
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case SCR_ ##N + 1: s->scr.N = (s->scr.N & ~(0xff << 8)) | (value & (0xff << 8)); break; \
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case SCR_ ##N + 2: s->scr.N = (s->scr.N & ~(0xff << 16)) | (value & (0xff << 16)); break; \
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case SCR_ ##N + 3: s->scr.N = (s->scr.N & ~(0xff << 24)) | (value & (0xff << 24)); break;
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#define SCR_REG_A(N) \
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case SCR_ ##N(0): s->scr.N[0] = value; break; \
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case SCR_ ##N(1): s->scr.N[1] = value; break; \
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case SCR_ ##N(2): s->scr.N[2] = value; break
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static void tc6393xb_writeb(void *opaque, target_phys_addr_t addr, uint32_t value)
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{
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struct tc6393xb_s *s = opaque;
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addr -= s->target_base;
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switch (addr) {
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SCR_REG_B(ISR);
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SCR_REG_B(IMR);
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SCR_REG_B(IRR);
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SCR_REG_W(GPER);
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SCR_REG_A(GPI_SR);
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SCR_REG_A(GPI_IMR);
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SCR_REG_A(GPI_EDER);
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SCR_REG_A(GPI_LIR);
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case SCR_GPO_DSR(0):
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case SCR_GPO_DSR(1):
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case SCR_GPO_DSR(2):
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s->gpio_level = (s->gpio_level & ~(0xff << ((addr - SCR_GPO_DSR(0))*8))) | ((value & 0xff) << ((addr - SCR_GPO_DSR(0))*8));
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tc6393xb_gpio_handler_update(s);
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break;
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case SCR_GPO_DOECR(0):
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case SCR_GPO_DOECR(1):
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case SCR_GPO_DOECR(2):
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s->gpio_dir = (s->gpio_dir & ~(0xff << ((addr - SCR_GPO_DOECR(0))*8))) | ((value & 0xff) << ((addr - SCR_GPO_DOECR(0))*8));
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tc6393xb_gpio_handler_update(s);
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break;
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SCR_REG_A(GP_IARCR);
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SCR_REG_A(GP_IARLCR);
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SCR_REG_A(GPI_BCR);
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SCR_REG_W(GPA_IARCR);
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SCR_REG_W(GPA_IARLCR);
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SCR_REG_W(CCR);
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SCR_REG_W(PLL2CR);
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SCR_REG_L(PLL1CR);
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SCR_REG_B(DIARCR);
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SCR_REG_B(DBOCR);
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SCR_REG_B(FER);
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SCR_REG_W(MCR);
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SCR_REG_B(CONFIG);
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SCR_REG_B(DEBUG);
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default:
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fprintf(stderr, "tc6393xb: unhandled write at %08x: %02x\n",
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(uint32_t) addr, value & 0xff);
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break;
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}
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}
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#undef SCR_REG_B
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#undef SCR_REG_W
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#undef SCR_REG_L
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#undef SCR_REG_A
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static uint32_t tc6393xb_readw(void *opaque, target_phys_addr_t addr)
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{
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return (tc6393xb_readb(opaque, addr) & 0xff) |
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(tc6393xb_readb(opaque, addr + 1) << 8);
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}
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static uint32_t tc6393xb_readl(void *opaque, target_phys_addr_t addr)
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{
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return (tc6393xb_readb(opaque, addr) & 0xff) |
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((tc6393xb_readb(opaque, addr + 1) & 0xff) << 8) |
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((tc6393xb_readb(opaque, addr + 2) & 0xff) << 16) |
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((tc6393xb_readb(opaque, addr + 3) & 0xff) << 24);
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}
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static void tc6393xb_writew(void *opaque, target_phys_addr_t addr, uint32_t value)
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{
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tc6393xb_writeb(opaque, addr, value);
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tc6393xb_writeb(opaque, addr + 1, value >> 8);
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}
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static void tc6393xb_writel(void *opaque, target_phys_addr_t addr, uint32_t value)
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{
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tc6393xb_writeb(opaque, addr, value);
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tc6393xb_writeb(opaque, addr + 1, value >> 8);
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tc6393xb_writeb(opaque, addr + 2, value >> 16);
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tc6393xb_writeb(opaque, addr + 3, value >> 24);
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}
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struct tc6393xb_s *tc6393xb_init(uint32_t base, qemu_irq irq)
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{
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int iomemtype;
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struct tc6393xb_s *s;
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CPUReadMemoryFunc *tc6393xb_readfn[] = {
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tc6393xb_readb,
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tc6393xb_readw,
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tc6393xb_readl,
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};
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CPUWriteMemoryFunc *tc6393xb_writefn[] = {
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tc6393xb_writeb,
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tc6393xb_writew,
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tc6393xb_writel,
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};
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s = (struct tc6393xb_s *) qemu_mallocz(sizeof(struct tc6393xb_s));
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s->target_base = base;
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s->gpio_in = qemu_allocate_irqs(tc6393xb_gpio_set, s, TC6393XB_GPIOS);
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iomemtype = cpu_register_io_memory(0, tc6393xb_readfn,
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tc6393xb_writefn, s);
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cpu_register_physical_memory(s->target_base, 0x200000, iomemtype);
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return s;
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}
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