Peter Maydell 7995206d05 hw/intc/arm_gic: Fix handling of GICD_ITARGETSR ... The GICD_ITARGETSR implementation still has some 11MPCore behaviour that we were incorrectly using in our GICv1 and GICv2 implementations for the case where the interrupt number is less than GIC_INTERNAL. The desired behaviour here is: * for 11MPCore: RAZ/WI for irqs 0..28; read a number matching the CPU doing the read for irqs 29..31 * for GICv1 and v2: RAZ/WI if uniprocessor; otherwise read a number matching the CPU doing the read for all irqs < 32 Stop squashing GICD_ITARGETSR to 0 for IRQs 0..28 unless this is an 11MPCore GIC. Reported-by: Jan Kiszka <jan.kiszka@web.de> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Luc Michel <luc.michel@greensocs.com> Message-id: 20180712154152.32183-3-peter.maydell@linaro.org		2018-07-16 17:18:41 +01:00
..
allwinner-a10-pic.c
apic_common.c
apic.c
arm_gic_common.c
arm_gic_kvm.c
arm_gic.c	hw/intc/arm_gic: Fix handling of GICD_ITARGETSR	2018-07-16 17:18:41 +01:00
arm_gicv2m.c
arm_gicv3_common.c
arm_gicv3_cpuif.c
arm_gicv3_dist.c
arm_gicv3_its_common.c
arm_gicv3_its_kvm.c
arm_gicv3_kvm.c
arm_gicv3_redist.c
arm_gicv3.c
armv7m_nvic.c
aspeed_vic.c
bcm2835_ic.c
bcm2836_control.c
etraxfs_pic.c
exynos4210_combiner.c
exynos4210_gic.c
gic_internal.h
gicv3_internal.h
grlib_irqmp.c
heathrow_pic.c
i8259_common.c
i8259.c
imx_avic.c
imx_gpcv2.c
intc.c
ioapic_common.c
ioapic.c
lm32_pic.c
Makefile.objs
mips_gic.c
nios2_iic.c
omap_intc.c
ompic.c
openpic_kvm.c
openpic.c
pl190.c
puv3_intc.c
realview_gic.c
s390_flic_kvm.c
s390_flic.c
sh_intc.c
slavio_intctl.c
trace-events
vgic_common.h
xics_kvm.c
xics_pnv.c
xics_spapr.c
xics.c
xilinx_intc.c
xlnx-pmu-iomod-intc.c
xlnx-zynqmp-ipi.c