Richard Henderson fbf59aad17 accel/tcg: Introduce tb_pc and log_pc ... The availability of tb->pc will shortly be conditional. Introduce accessor functions to minimize ifdefs. Pass around a known pc to places like tcg_gen_code, where the caller must already have the value. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>		2022-10-04 12:13:12 -07:00
..
insn_trans	target/riscv: rvv-1.0: vf[w]redsum distinguish between ordered/unordered	2022-09-27 11:23:57 +10:00
arch_dump.c
bitmanip_helper.c
common-semi-target.h
cpu_bits.h	target/riscv: debug: Introduce tinfo CSR	2022-09-27 11:23:57 +10:00
cpu_helper.c	target/riscv: Honour -semihosting-config userspace=on and enable=on	2022-09-13 17:18:21 +01:00
cpu_user.h
cpu-param.h
cpu.c	accel/tcg: Introduce tb_pc and log_pc	2022-10-04 12:13:12 -07:00
cpu.h	target/riscv: debug: Introduce tdata1, tdata2, and tdata3 CSRs	2022-09-27 11:23:57 +10:00
crypto_helper.c
csr.c	target/riscv: debug: Introduce tinfo CSR	2022-09-27 11:23:57 +10:00
debug.c	target/riscv: debug: Add initial support of type 6 trigger	2022-09-27 11:23:57 +10:00
debug.h	target/riscv: debug: Add initial support of type 6 trigger	2022-09-27 11:23:57 +10:00
fpu_helper.c
gdbstub.c	target/riscv: Check the correct exception cause in vector GDB stub	2022-09-27 07:04:38 +10:00
helper.h	target/riscv: rvv-1.0: vf[w]redsum distinguish between ordered/unordered	2022-09-27 11:23:57 +10:00
insn16.decode
insn32.decode	target/riscv: rvv-1.0: vf[w]redsum distinguish between ordered/unordered	2022-09-27 11:23:57 +10:00
instmap.h
internals.h
Kconfig
kvm_riscv.h
kvm-stub.c
kvm.c
m128_helper.c
machine.c	target/riscv: debug: Introduce tdata1, tdata2, and tdata3 CSRs	2022-09-27 11:23:57 +10:00
meson.build	target/riscv: Add stimecmp support	2022-09-07 09:19:15 +02:00
monitor.c
op_helper.c
pmp.c
pmp.h
pmu.c	hw/riscv: virt: Add PMU DT node to the device tree	2022-09-07 09:19:15 +02:00
pmu.h	hw/riscv: virt: Add PMU DT node to the device tree	2022-09-07 09:19:15 +02:00
sbi_ecall_interface.h
time_helper.c	target/riscv: Add vstimecmp support	2022-09-07 09:19:15 +02:00
time_helper.h	target/riscv: Add stimecmp support	2022-09-07 09:19:15 +02:00
trace-events
trace.h
translate.c	target/riscv: Honour -semihosting-config userspace=on and enable=on	2022-09-13 17:18:21 +01:00
vector_helper.c	target/riscv: rvv-1.0: vf[w]redsum distinguish between ordered/unordered	2022-09-27 11:23:57 +10:00
XVentanaCondOps.decode