eb1e7c3e51
This implementation doesn't include ring priority, TCP/IP Off-Load, QoS. Signed-off-by: Fabien Chouteau <chouteau@adacore.com> Signed-off-by: Alexander Graf <agraf@suse.de>
147 lines
3.7 KiB
C
147 lines
3.7 KiB
C
/*
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* QEMU Freescale eTSEC Emulator
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*
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* Copyright (c) 2011-2013 AdaCore
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "etsec.h"
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#include "registers.h"
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/* #define DEBUG_MIIM */
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#define MIIM_CONTROL 0
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#define MIIM_STATUS 1
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#define MIIM_PHY_ID_1 2
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#define MIIM_PHY_ID_2 3
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#define MIIM_T2_STATUS 10
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#define MIIM_EXT_STATUS 15
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static void miim_read_cycle(eTSEC *etsec)
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{
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uint8_t phy;
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uint8_t addr;
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uint16_t value;
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phy = (etsec->regs[MIIMADD].value >> 8) & 0x1F;
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(void)phy; /* Unreferenced */
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addr = etsec->regs[MIIMADD].value & 0x1F;
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switch (addr) {
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case MIIM_CONTROL:
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value = etsec->phy_control;
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break;
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case MIIM_STATUS:
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value = etsec->phy_status;
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break;
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case MIIM_T2_STATUS:
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value = 0x1800; /* Local and remote receivers OK */
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break;
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default:
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value = 0x0;
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break;
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};
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#ifdef DEBUG_MIIM
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qemu_log("%s phy:%d addr:0x%x value:0x%x\n", __func__, phy, addr, value);
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#endif
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etsec->regs[MIIMSTAT].value = value;
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}
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static void miim_write_cycle(eTSEC *etsec)
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{
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uint8_t phy;
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uint8_t addr;
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uint16_t value;
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phy = (etsec->regs[MIIMADD].value >> 8) & 0x1F;
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(void)phy; /* Unreferenced */
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addr = etsec->regs[MIIMADD].value & 0x1F;
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value = etsec->regs[MIIMCON].value & 0xffff;
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#ifdef DEBUG_MIIM
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qemu_log("%s phy:%d addr:0x%x value:0x%x\n", __func__, phy, addr, value);
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#endif
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switch (addr) {
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case MIIM_CONTROL:
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etsec->phy_control = value & ~(0x8100);
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break;
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default:
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break;
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};
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}
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void etsec_write_miim(eTSEC *etsec,
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eTSEC_Register *reg,
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uint32_t reg_index,
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uint32_t value)
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{
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switch (reg_index) {
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case MIIMCOM:
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/* Read and scan cycle */
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if ((!(reg->value & MIIMCOM_READ)) && (value & MIIMCOM_READ)) {
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/* Read */
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miim_read_cycle(etsec);
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}
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reg->value = value;
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break;
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case MIIMCON:
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reg->value = value & 0xffff;
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miim_write_cycle(etsec);
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break;
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default:
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/* Default handling */
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switch (reg->access) {
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case ACC_RW:
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case ACC_WO:
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reg->value = value;
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break;
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case ACC_W1C:
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reg->value &= ~value;
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break;
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case ACC_RO:
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default:
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/* Read Only or Unknown register */
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break;
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}
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}
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}
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void etsec_miim_link_status(eTSEC *etsec, NetClientState *nc)
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{
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/* Set link status */
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if (nc->link_down) {
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etsec->phy_status &= ~MII_SR_LINK_STATUS;
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} else {
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etsec->phy_status |= MII_SR_LINK_STATUS;
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}
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}
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