45d8cdbd56
Added basic qtests for FSI model. Signed-off-by: Ninad Palsule <ninad@linux.ibm.com> Acked-by: Thomas Huth <thuth@redhat.com> [ clg: aspeed-fsi-test.c -> aspeed_fsi-test.c to match other filenames ] Signed-off-by: Cédric Le Goater <clg@kaod.org>
206 lines
6.6 KiB
C
206 lines
6.6 KiB
C
/*
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* QTest testcases for IBM's Flexible Service Interface (FSI)
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*
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* Copyright (c) 2023 IBM Corporation
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*
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* Authors:
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* Ninad Palsule <ninad@linux.ibm.com>
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*/
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#include "qemu/osdep.h"
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#include <glib/gstdio.h>
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#include "qemu/module.h"
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#include "libqtest-single.h"
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/* Registers from ast2600 specifications */
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#define ASPEED_FSI_ENGINER_TRIGGER 0x04
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#define ASPEED_FSI_OPB0_BUS_SELECT 0x10
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#define ASPEED_FSI_OPB1_BUS_SELECT 0x28
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#define ASPEED_FSI_OPB0_RW_DIRECTION 0x14
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#define ASPEED_FSI_OPB1_RW_DIRECTION 0x2c
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#define ASPEED_FSI_OPB0_XFER_SIZE 0x18
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#define ASPEED_FSI_OPB1_XFER_SIZE 0x30
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#define ASPEED_FSI_OPB0_BUS_ADDR 0x1c
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#define ASPEED_FSI_OPB1_BUS_ADDR 0x34
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#define ASPEED_FSI_INTRRUPT_CLEAR 0x40
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#define ASPEED_FSI_INTRRUPT_STATUS 0x48
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#define ASPEED_FSI_OPB0_BUS_STATUS 0x80
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#define ASPEED_FSI_OPB1_BUS_STATUS 0x8c
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#define ASPEED_FSI_OPB0_READ_DATA 0x84
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#define ASPEED_FSI_OPB1_READ_DATA 0x90
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/*
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* FSI Base addresses from the ast2600 specifications.
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*/
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#define AST2600_OPB_FSI0_BASE_ADDR 0x1e79b000
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#define AST2600_OPB_FSI1_BASE_ADDR 0x1e79b100
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static uint32_t aspeed_fsi_base_addr;
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static uint32_t aspeed_fsi_readl(QTestState *s, uint32_t reg)
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{
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return qtest_readl(s, aspeed_fsi_base_addr + reg);
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}
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static void aspeed_fsi_writel(QTestState *s, uint32_t reg, uint32_t val)
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{
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qtest_writel(s, aspeed_fsi_base_addr + reg, val);
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}
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/* Setup base address and select register */
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static void test_fsi_setup(QTestState *s, uint32_t base_addr)
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{
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uint32_t curval;
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aspeed_fsi_base_addr = base_addr;
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/* Set the base select register */
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if (base_addr == AST2600_OPB_FSI0_BASE_ADDR) {
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/* Unselect FSI1 */
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aspeed_fsi_writel(s, ASPEED_FSI_OPB1_BUS_SELECT, 0x0);
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curval = aspeed_fsi_readl(s, ASPEED_FSI_OPB1_BUS_SELECT);
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g_assert_cmpuint(curval, ==, 0x0);
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/* Select FSI0 */
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aspeed_fsi_writel(s, ASPEED_FSI_OPB0_BUS_SELECT, 0x1);
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curval = aspeed_fsi_readl(s, ASPEED_FSI_OPB0_BUS_SELECT);
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g_assert_cmpuint(curval, ==, 0x1);
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} else if (base_addr == AST2600_OPB_FSI1_BASE_ADDR) {
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/* Unselect FSI0 */
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aspeed_fsi_writel(s, ASPEED_FSI_OPB0_BUS_SELECT, 0x0);
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curval = aspeed_fsi_readl(s, ASPEED_FSI_OPB0_BUS_SELECT);
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g_assert_cmpuint(curval, ==, 0x0);
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/* Select FSI1 */
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aspeed_fsi_writel(s, ASPEED_FSI_OPB1_BUS_SELECT, 0x1);
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curval = aspeed_fsi_readl(s, ASPEED_FSI_OPB1_BUS_SELECT);
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g_assert_cmpuint(curval, ==, 0x1);
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} else {
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g_assert_not_reached();
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}
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}
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static void test_fsi_reg_change(QTestState *s, uint32_t reg, uint32_t newval)
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{
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uint32_t base;
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uint32_t curval;
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base = aspeed_fsi_readl(s, reg);
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aspeed_fsi_writel(s, reg, newval);
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curval = aspeed_fsi_readl(s, reg);
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g_assert_cmpuint(curval, ==, newval);
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aspeed_fsi_writel(s, reg, base);
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curval = aspeed_fsi_readl(s, reg);
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g_assert_cmpuint(curval, ==, base);
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}
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static void test_fsi0_master_regs(const void *data)
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{
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QTestState *s = (QTestState *)data;
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test_fsi_setup(s, AST2600_OPB_FSI0_BASE_ADDR);
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test_fsi_reg_change(s, ASPEED_FSI_OPB0_RW_DIRECTION, 0xF3F4F514);
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test_fsi_reg_change(s, ASPEED_FSI_OPB0_XFER_SIZE, 0xF3F4F518);
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test_fsi_reg_change(s, ASPEED_FSI_OPB0_BUS_ADDR, 0xF3F4F51c);
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test_fsi_reg_change(s, ASPEED_FSI_INTRRUPT_CLEAR, 0xF3F4F540);
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test_fsi_reg_change(s, ASPEED_FSI_INTRRUPT_STATUS, 0xF3F4F548);
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test_fsi_reg_change(s, ASPEED_FSI_OPB0_BUS_STATUS, 0xF3F4F580);
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test_fsi_reg_change(s, ASPEED_FSI_OPB0_READ_DATA, 0xF3F4F584);
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}
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static void test_fsi1_master_regs(const void *data)
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{
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QTestState *s = (QTestState *)data;
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test_fsi_setup(s, AST2600_OPB_FSI1_BASE_ADDR);
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test_fsi_reg_change(s, ASPEED_FSI_OPB1_RW_DIRECTION, 0xF3F4F514);
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test_fsi_reg_change(s, ASPEED_FSI_OPB1_XFER_SIZE, 0xF3F4F518);
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test_fsi_reg_change(s, ASPEED_FSI_OPB1_BUS_ADDR, 0xF3F4F51c);
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test_fsi_reg_change(s, ASPEED_FSI_INTRRUPT_CLEAR, 0xF3F4F540);
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test_fsi_reg_change(s, ASPEED_FSI_INTRRUPT_STATUS, 0xF3F4F548);
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test_fsi_reg_change(s, ASPEED_FSI_OPB1_BUS_STATUS, 0xF3F4F580);
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test_fsi_reg_change(s, ASPEED_FSI_OPB1_READ_DATA, 0xF3F4F584);
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}
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static void test_fsi0_getcfam_addr0(const void *data)
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{
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QTestState *s = (QTestState *)data;
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uint32_t curval;
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test_fsi_setup(s, AST2600_OPB_FSI0_BASE_ADDR);
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/* Master access direction read */
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aspeed_fsi_writel(s, ASPEED_FSI_OPB0_RW_DIRECTION, 0x1);
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/* word */
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aspeed_fsi_writel(s, ASPEED_FSI_OPB0_XFER_SIZE, 0x3);
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/* Address */
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aspeed_fsi_writel(s, ASPEED_FSI_OPB0_BUS_ADDR, 0xa0000000);
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aspeed_fsi_writel(s, ASPEED_FSI_INTRRUPT_CLEAR, 0x1);
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aspeed_fsi_writel(s, ASPEED_FSI_ENGINER_TRIGGER, 0x1);
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curval = aspeed_fsi_readl(s, ASPEED_FSI_INTRRUPT_STATUS);
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g_assert_cmpuint(curval, ==, 0x10000);
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curval = aspeed_fsi_readl(s, ASPEED_FSI_OPB0_BUS_STATUS);
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g_assert_cmpuint(curval, ==, 0x0);
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curval = aspeed_fsi_readl(s, ASPEED_FSI_OPB0_READ_DATA);
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g_assert_cmpuint(curval, ==, 0x152d02c0);
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}
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static void test_fsi1_getcfam_addr0(const void *data)
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{
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QTestState *s = (QTestState *)data;
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uint32_t curval;
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test_fsi_setup(s, AST2600_OPB_FSI1_BASE_ADDR);
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/* Master access direction read */
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aspeed_fsi_writel(s, ASPEED_FSI_OPB1_RW_DIRECTION, 0x1);
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aspeed_fsi_writel(s, ASPEED_FSI_OPB1_XFER_SIZE, 0x3);
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aspeed_fsi_writel(s, ASPEED_FSI_OPB1_BUS_ADDR, 0xa0000000);
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aspeed_fsi_writel(s, ASPEED_FSI_INTRRUPT_CLEAR, 0x1);
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aspeed_fsi_writel(s, ASPEED_FSI_ENGINER_TRIGGER, 0x1);
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curval = aspeed_fsi_readl(s, ASPEED_FSI_INTRRUPT_STATUS);
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g_assert_cmpuint(curval, ==, 0x20000);
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curval = aspeed_fsi_readl(s, ASPEED_FSI_OPB1_BUS_STATUS);
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g_assert_cmpuint(curval, ==, 0x0);
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curval = aspeed_fsi_readl(s, ASPEED_FSI_OPB1_READ_DATA);
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g_assert_cmpuint(curval, ==, 0x152d02c0);
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}
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int main(int argc, char **argv)
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{
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int ret = -1;
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QTestState *s;
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g_test_init(&argc, &argv, NULL);
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s = qtest_init("-machine ast2600-evb ");
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/* Tests for OPB/FSI0 */
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qtest_add_data_func("/aspeed-fsi-test/test_fsi0_master_regs", s,
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test_fsi0_master_regs);
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qtest_add_data_func("/aspeed-fsi-test/test_fsi0_getcfam_addr0", s,
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test_fsi0_getcfam_addr0);
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/* Tests for OPB/FSI1 */
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qtest_add_data_func("/aspeed-fsi-test/test_fsi1_master_regs", s,
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test_fsi1_master_regs);
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qtest_add_data_func("/aspeed-fsi-test/test_fsi1_getcfam_addr0", s,
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test_fsi1_getcfam_addr0);
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ret = g_test_run();
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qtest_quit(s);
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return ret;
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}
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