162 lines
5.2 KiB
C
162 lines
5.2 KiB
C
/*
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* QEMU Grackle (heathrow PPC) PCI host
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*
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* Copyright (c) 2006 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "vl.h"
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typedef target_phys_addr_t pci_addr_t;
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#include "pci_host.h"
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typedef PCIHostState GrackleState;
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static void pci_grackle_config_writel (void *opaque, target_phys_addr_t addr,
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uint32_t val)
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{
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GrackleState *s = opaque;
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#ifdef TARGET_WORDS_BIGENDIAN
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val = bswap32(val);
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#endif
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s->config_reg = val;
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}
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static uint32_t pci_grackle_config_readl (void *opaque, target_phys_addr_t addr)
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{
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GrackleState *s = opaque;
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uint32_t val;
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val = s->config_reg;
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#ifdef TARGET_WORDS_BIGENDIAN
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val = bswap32(val);
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#endif
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return val;
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}
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static CPUWriteMemoryFunc *pci_grackle_config_write[] = {
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&pci_grackle_config_writel,
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&pci_grackle_config_writel,
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&pci_grackle_config_writel,
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};
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static CPUReadMemoryFunc *pci_grackle_config_read[] = {
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&pci_grackle_config_readl,
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&pci_grackle_config_readl,
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&pci_grackle_config_readl,
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};
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static CPUWriteMemoryFunc *pci_grackle_write[] = {
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&pci_host_data_writeb,
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&pci_host_data_writew,
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&pci_host_data_writel,
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};
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static CPUReadMemoryFunc *pci_grackle_read[] = {
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&pci_host_data_readb,
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&pci_host_data_readw,
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&pci_host_data_readl,
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};
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/* Don't know if this matches real hardware, but it agrees with OHW. */
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static int pci_grackle_map_irq(PCIDevice *pci_dev, int irq_num)
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{
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return (irq_num + (pci_dev->devfn >> 3)) & 3;
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}
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static void pci_grackle_set_irq(void *pic, int irq_num, int level)
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{
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heathrow_pic_set_irq(pic, irq_num + 8, level);
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}
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PCIBus *pci_grackle_init(uint32_t base, void *pic)
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{
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GrackleState *s;
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PCIDevice *d;
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int pci_mem_config, pci_mem_data;
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s = qemu_mallocz(sizeof(GrackleState));
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s->bus = pci_register_bus(pci_grackle_set_irq, pci_grackle_map_irq,
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pic, 0, 0);
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pci_mem_config = cpu_register_io_memory(0, pci_grackle_config_read,
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pci_grackle_config_write, s);
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pci_mem_data = cpu_register_io_memory(0, pci_grackle_read,
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pci_grackle_write, s);
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cpu_register_physical_memory(base, 0x1000, pci_mem_config);
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cpu_register_physical_memory(base + 0x00200000, 0x1000, pci_mem_data);
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d = pci_register_device(s->bus, "Grackle host bridge", sizeof(PCIDevice),
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0, NULL, NULL);
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d->config[0x00] = 0x57; // vendor_id
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d->config[0x01] = 0x10;
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d->config[0x02] = 0x02; // device_id
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d->config[0x03] = 0x00;
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d->config[0x08] = 0x00; // revision
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d->config[0x09] = 0x01;
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d->config[0x0a] = 0x00; // class_sub = host
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d->config[0x0b] = 0x06; // class_base = PCI_bridge
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d->config[0x0e] = 0x00; // header_type
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d->config[0x18] = 0x00; // primary_bus
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d->config[0x19] = 0x01; // secondary_bus
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d->config[0x1a] = 0x00; // subordinate_bus
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d->config[0x1c] = 0x00;
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d->config[0x1d] = 0x00;
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d->config[0x20] = 0x00; // memory_base
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d->config[0x21] = 0x00;
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d->config[0x22] = 0x01; // memory_limit
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d->config[0x23] = 0x00;
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d->config[0x24] = 0x00; // prefetchable_memory_base
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d->config[0x25] = 0x00;
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d->config[0x26] = 0x00; // prefetchable_memory_limit
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d->config[0x27] = 0x00;
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#if 0
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/* PCI2PCI bridge same values as PearPC - check this */
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d->config[0x00] = 0x11; // vendor_id
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d->config[0x01] = 0x10;
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d->config[0x02] = 0x26; // device_id
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d->config[0x03] = 0x00;
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d->config[0x08] = 0x02; // revision
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d->config[0x0a] = 0x04; // class_sub = pci2pci
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d->config[0x0b] = 0x06; // class_base = PCI_bridge
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d->config[0x0e] = 0x01; // header_type
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d->config[0x18] = 0x0; // primary_bus
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d->config[0x19] = 0x1; // secondary_bus
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d->config[0x1a] = 0x1; // subordinate_bus
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d->config[0x1c] = 0x10; // io_base
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d->config[0x1d] = 0x20; // io_limit
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d->config[0x20] = 0x80; // memory_base
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d->config[0x21] = 0x80;
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d->config[0x22] = 0x90; // memory_limit
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d->config[0x23] = 0x80;
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d->config[0x24] = 0x00; // prefetchable_memory_base
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d->config[0x25] = 0x84;
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d->config[0x26] = 0x00; // prefetchable_memory_limit
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d->config[0x27] = 0x85;
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#endif
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return s->bus;
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}
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