94 lines
3.3 KiB
C
94 lines
3.3 KiB
C
#if !defined (__QEMU_MIPS_DEFS_H__)
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#define __QEMU_MIPS_DEFS_H__
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/* If we want to use 64 bits host regs... */
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//#define USE_64BITS_REGS
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/* If we want to use host float regs... */
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//#define USE_HOST_FLOAT_REGS
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#define MIPS_R4Kc 0x00018000
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#define MIPS_R4Kp 0x00018300
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/* Emulate MIPS R4Kc for now */
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#define MIPS_CPU MIPS_R4Kc
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#if (MIPS_CPU == MIPS_R4Kc)
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/* 32 bits target */
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#undef MIPS_HAS_MIPS64
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//#define MIPS_HAS_MIPS64 1
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/* real pages are variable size... */
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#define TARGET_PAGE_BITS 12
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/* Uses MIPS R4Kx enhancements to MIPS32 architecture */
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#define MIPS_USES_R4K_EXT
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/* Uses MIPS R4Kc TLB model */
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#define MIPS_USES_R4K_TLB
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#define MIPS_TLB_NB 16
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#define MIPS_TLB_MAX 128
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/* basic FPU register support */
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#define MIPS_USES_FPU 1
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/* Define a implementation number of 1.
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* Define a major version 1, minor version 0.
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*/
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#define MIPS_FCR0 ((0 << 16) | (1 << 8) | (1 << 4) | 0)
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/* Have config1, is MIPS32R1, uses TLB, no virtual icache,
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uncached coherency */
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#define MIPS_CONFIG0_1 \
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((1 << CP0C0_M) | (0x0 << CP0C0_K23) | (0x0 << CP0C0_KU) | \
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(0x0 << CP0C0_AT) | (0x0 << CP0C0_AR) | (0x1 << CP0C0_MT) | \
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(0x2 << CP0C0_K0))
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#ifdef TARGET_WORDS_BIGENDIAN
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#define MIPS_CONFIG0 (MIPS_CONFIG0_1 | (1 << CP0C0_BE))
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#else
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#define MIPS_CONFIG0 MIPS_CONFIG0_1
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#endif
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/* Have config2, 16 TLB entries, 64 sets Icache, 16 bytes Icache line,
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2-way Icache, 64 sets Dcache, 16 bytes Dcache line, 2-way Dcache,
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no coprocessor2 attached, no MDMX support attached,
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no performance counters, watch registers present,
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no code compression, EJTAG present, FPU enable bit depending on
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MIPS_USES_FPU */
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#define MIPS_CONFIG1_1 \
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((1 << CP0C1_M) | ((MIPS_TLB_NB - 1) << CP0C1_MMU) | \
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(0x0 << CP0C1_IS) | (0x3 << CP0C1_IL) | (0x1 << CP0C1_IA) | \
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(0x0 << CP0C1_DS) | (0x3 << CP0C1_DL) | (0x1 << CP0C1_DA) | \
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(0 << CP0C1_C2) | (0 << CP0C1_MD) | (0 << CP0C1_PC) | \
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(1 << CP0C1_WR) | (0 << CP0C1_CA) | (1 << CP0C1_EP))
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#ifdef MIPS_USES_FPU
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#define MIPS_CONFIG1 (MIPS_CONFIG1_1 | (1 << CP0C1_FP))
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#else
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#define MIPS_CONFIG1 (MIPS_CONFIG1_1 | (0 << CP0C1_FP))
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#endif
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/* Have config3, no tertiary/secondary caches implemented */
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#define MIPS_CONFIG2 \
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((1 << CP0C2_M))
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/* No config4, no DSP ASE, no large physaddr,
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no external interrupt controller, no vectored interupts,
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no 1kb pages, no MT ASE, no SmartMIPS ASE, no trace logic */
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#define MIPS_CONFIG3 \
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((0 << CP0C3_M) | (0 << CP0C3_DSPP) | (0 << CP0C3_LPA) | \
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(0 << CP0C3_VEIC) | (0 << CP0C3_VInt) | (0 << CP0C3_SP) | \
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(0 << CP0C3_MT) | (0 << CP0C3_SM) | (0 << CP0C3_TL))
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#elif (MIPS_CPU == MIPS_R4Kp)
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/* 32 bits target */
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#undef MIPS_HAS_MIPS64
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/* real pages are variable size... */
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#define TARGET_PAGE_BITS 12
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/* Uses MIPS R4Kx enhancements to MIPS32 architecture */
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#define MIPS_USES_R4K_EXT
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/* Uses MIPS R4Km FPM MMU model */
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#define MIPS_USES_R4K_FPM
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#else
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#error "MIPS CPU not defined"
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/* Reminder for other flags */
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//#undef MIPS_HAS_MIPS64
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//#define MIPS_USES_FPU
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#endif
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#ifdef MIPS_HAS_MIPS64
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#define TARGET_LONG_BITS 64
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#else
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#define TARGET_LONG_BITS 32
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#endif
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#endif /* !defined (__QEMU_MIPS_DEFS_H__) */
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