Mikhail Tyutin 0d581506de Fix incorrect register name in disassembler for fmv,fabs,fneg instructions ...

Fix incorrect register name in RISC-V disassembler for fmv,fabs,fneg instructions

Signed-off-by: Mikhail Tyutin <m.tyutin@yadro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <3454991f-7f64-24c3-9a36-f5fa2cc389e1@yadro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

2023-03-14 16:36:43 +10:00

..

alpha.c

…

capstone.c

disas: use result of ->read_memory_func

2022-10-06 11:53:40 +01:00

cris.c

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hexagon.c

Hexagon (disas/hexagon.c) fix memory leak for early exit cases

2021-08-12 09:06:05 -05:00

hppa.c

disas/: fix some comment spelling errors

2020-09-17 20:40:08 +02:00

m68k.c

disas/: fix some comment spelling errors

2020-09-17 20:40:08 +02:00

meson.build

mips: Always include nanomips disassembler

2023-01-13 16:22:53 +01:00

microblaze.c

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mips.c

disas/mips: Fix branch displacement for BEQZC and BNEZC

2022-10-31 11:32:07 +01:00

nanomips.c

disas/nanomips: Tidy read for 48-bit opcodes

2022-11-08 01:04:25 +01:00

nios2.c

disas/nios2: Simplify endianess conversion

2021-10-22 18:07:30 +02:00

riscv.c

Fix incorrect register name in disassembler for fmv,fabs,fneg instructions

2023-03-14 16:36:43 +10:00

sh4.c

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sparc.c

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xtensa.c

…