Peter Maydell 482b61844a target-arm queue: ... * GICv3 emulation -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABCAAGBQJXZAgcAAoJEDwlJe0UNgze+xMP/371ot4BlUUkVSKIBaSuq3pd C5jqozcHo8+HObIdGJ2sP6ksiL5tdOFyhjSGm9jU4ERMGepzMI7Ztt1Ox2IGMvK1 +1dG2pdXZZnFa9RmYXZ+tQQA+th/bvAL3utXnuAq/rMuXCG8BB5Q3o5R88W2P9IY Xkr3RHSG57Sy5bR85TGiJDnANmS7VdpCK8T8CjKLye9XbQ7jec52jN5JKl4Q1H9y KWGJu/Q0ffJGePZa4aZXtgVQSVFyqXXRj+cZKV3lrbztfVoC76TfG/ga0djPuCVH HKCZLADiM1LahTrlMtEWsne3zkwyxwWdidDRshOPzM0gyoiPOPS8Im9n9liUEE+B 4igXd7xS+UXlXHJqYlGdZOQV8EU4123hEkrMY/eI50c/UYzCV281YBlVzL+zD+13 WDIotuX/yF1Rt//MUPeHOQFauRgYa8epFNSHatPGyfU7HFxR+9ErB1IOR79atZAs wbaA0FvJV/TeBTEZ41YhW21FbdfK4tGztEIZyz5RL8IPp6JXtWi3Ir/zzPcdD6xm FjKaMoXpNjuvE2KZKFpeLiNuNeOIRhdVjiwAI4B/eiSLJ1gHEPzuhnMm8uVF/7uf LWt73h+b1pXhcWtxLS4cgxza+QSfs5PDXPhO8gisxiqE86mmuJBx22UvlHoN2iDq jN8TGsubo/qqmEkexVBX =1ZVZ -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20160617' into staging target-arm queue: * GICv3 emulation # gpg: Signature made Fri 17 Jun 2016 15:24:28 BST # gpg: using RSA key 0x3C2525ED14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" # gpg: aka "Peter Maydell <pmaydell@gmail.com>" # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20160617: (22 commits) ACPI: ARM: Present GIC version in MADT table hw/timer: Add value matching support to aspeed_timer target-arm/monitor.c: Advertise emulated GICv3 in capabilities target-arm/machine.c: Allow user to request GICv3 emulation hw/intc/arm_gicv3: Add IRQ handling CPU interface registers hw/intc/arm_gicv3: Implement CPU i/f SGI generation registers hw/intc/arm_gicv3: Implement gicv3_cpuif_update() hw/intc/arm_gicv3: Implement GICv3 CPU interface registers hw/intc/arm_gicv3: Implement gicv3_set_irq() hw/intc/arm_gicv3: Wire up distributor and redistributor MMIO regions hw/intc/arm_gicv3: Implement GICv3 redistributor registers hw/intc/arm_gicv3: Implement GICv3 distributor registers hw/intc/arm_gicv3: Implement functions to identify next pending irq hw/intc/arm_gicv3: ARM GICv3 device framework hw/intc/arm_gicv3: Add vmstate descriptors hw/intc/arm_gicv3: Move irq lines into GICv3CPUState structure hw/intc/arm_gicv3: Add state information target-arm: Add mp-affinity property for ARM CPU class target-arm: Provide hook to tell GICv3 about changes of security state target-arm: Define new arm_is_el3_or_mon() function ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>		2016-06-17 16:16:37 +01:00
..
block	nbd: Avoid magic number for NBD max name size	2016-06-16 18:39:05 +02:00
crypto	crypto: aes: always rename internal symbols	2016-06-13 12:41:17 +01:00
disas
exec	tb hash: track translated blocks with qht	2016-06-11 17:11:16 -07:00
fpu
hw	target-arm queue:	2016-06-17 16:16:37 +01:00
io
libdecnumber
migration	migration: Define VMSTATE_UINT64_2DARRAY	2016-06-17 15:23:51 +01:00
monitor
net	vhost-net: save & restore vring enable state	2016-06-17 03:28:03 +03:00
qapi
qemu	bitops.h: Implement half-shuffle and half-unshuffle ops	2016-06-17 15:23:51 +01:00
qom	qom: API to get instance_size of a type	2016-06-17 16:33:48 +10:00
standard-headers	linux-headers: update	2016-06-14 13:34:50 +02:00
sysemu	pc, pci, virtio: new features, cleanups, fixes	2016-06-17 11:25:46 +01:00
ui
elf.h	Add PowerPC AT_HWCAP2 definitions	2016-06-14 10:41:38 +10:00
glib-compat.h
qemu-common.h
qemu-io.h
trace-tcg.h
trace.h