7c979afd11
This relatively small architectural feature adds the following:
FIR.FREP: Read-only. If FREP=1, then Config5.FRE and Config5.UFE are
available.
Config5.FRE: When enabled all single-precision FP arithmetic instructions,
LWC1/LWXC1/MTC1, SWC1/SWXC1/MFC1 cause a Reserved Instructions
exception.
Config5.UFE: Allows user to write/read Config5.FRE using CTC1/CFC1
instructions.
Enable the feature in MIPS64R6-generic CPU.
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
851 lines
33 KiB
C
851 lines
33 KiB
C
/*
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* MIPS emulation for qemu: CPU initialisation routines.
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*
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* Copyright (c) 2004-2005 Jocelyn Mayer
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* Copyright (c) 2007 Herve Poussineau
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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/* CPU / CPU family specific config register values. */
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/* Have config1, uncached coherency */
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#define MIPS_CONFIG0 \
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((1U << CP0C0_M) | (0x2 << CP0C0_K0))
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/* Have config2, no coprocessor2 attached, no MDMX support attached,
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no performance counters, watch registers present,
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no code compression, EJTAG present, no FPU */
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#define MIPS_CONFIG1 \
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((1U << CP0C1_M) | \
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(0 << CP0C1_C2) | (0 << CP0C1_MD) | (0 << CP0C1_PC) | \
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(1 << CP0C1_WR) | (0 << CP0C1_CA) | (1 << CP0C1_EP) | \
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(0 << CP0C1_FP))
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/* Have config3, no tertiary/secondary caches implemented */
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#define MIPS_CONFIG2 \
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((1U << CP0C2_M))
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/* No config4, no DSP ASE, no large physaddr (PABITS),
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no external interrupt controller, no vectored interrupts,
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no 1kb pages, no SmartMIPS ASE, no trace logic */
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#define MIPS_CONFIG3 \
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((0 << CP0C3_M) | (0 << CP0C3_DSPP) | (0 << CP0C3_LPA) | \
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(0 << CP0C3_VEIC) | (0 << CP0C3_VInt) | (0 << CP0C3_SP) | \
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(0 << CP0C3_SM) | (0 << CP0C3_TL))
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#define MIPS_CONFIG4 \
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((0 << CP0C4_M))
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#define MIPS_CONFIG5 \
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((0 << CP0C5_M))
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/* MMU types, the first four entries have the same layout as the
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CP0C0_MT field. */
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enum mips_mmu_types {
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MMU_TYPE_NONE,
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MMU_TYPE_R4000,
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MMU_TYPE_RESERVED,
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MMU_TYPE_FMT,
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MMU_TYPE_R3000,
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MMU_TYPE_R6000,
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MMU_TYPE_R8000
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};
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struct mips_def_t {
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const char *name;
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int32_t CP0_PRid;
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int32_t CP0_Config0;
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int32_t CP0_Config1;
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int32_t CP0_Config2;
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int32_t CP0_Config3;
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int32_t CP0_Config4;
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int32_t CP0_Config4_rw_bitmask;
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int32_t CP0_Config5;
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int32_t CP0_Config5_rw_bitmask;
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int32_t CP0_Config6;
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int32_t CP0_Config7;
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target_ulong CP0_LLAddr_rw_bitmask;
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int CP0_LLAddr_shift;
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int32_t SYNCI_Step;
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int32_t CCRes;
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int32_t CP0_Status_rw_bitmask;
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int32_t CP0_TCStatus_rw_bitmask;
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int32_t CP0_SRSCtl;
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int32_t CP1_fcr0;
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int32_t MSAIR;
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int32_t SEGBITS;
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int32_t PABITS;
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int32_t CP0_SRSConf0_rw_bitmask;
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int32_t CP0_SRSConf0;
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int32_t CP0_SRSConf1_rw_bitmask;
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int32_t CP0_SRSConf1;
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int32_t CP0_SRSConf2_rw_bitmask;
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int32_t CP0_SRSConf2;
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int32_t CP0_SRSConf3_rw_bitmask;
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int32_t CP0_SRSConf3;
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int32_t CP0_SRSConf4_rw_bitmask;
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int32_t CP0_SRSConf4;
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int32_t CP0_PageGrain_rw_bitmask;
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int32_t CP0_PageGrain;
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int insn_flags;
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enum mips_mmu_types mmu_type;
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};
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/*****************************************************************************/
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/* MIPS CPU definitions */
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static const mips_def_t mips_defs[] =
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{
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{
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.name = "4Kc",
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.CP0_PRid = 0x00018000,
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.CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_R4000 << CP0C0_MT),
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.CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
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(0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
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(0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
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(0 << CP0C1_CA),
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.CP0_Config2 = MIPS_CONFIG2,
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.CP0_Config3 = MIPS_CONFIG3,
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.CP0_LLAddr_rw_bitmask = 0,
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.CP0_LLAddr_shift = 4,
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.SYNCI_Step = 32,
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.CCRes = 2,
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.CP0_Status_rw_bitmask = 0x1278FF17,
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.SEGBITS = 32,
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.PABITS = 32,
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.insn_flags = CPU_MIPS32,
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.mmu_type = MMU_TYPE_R4000,
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},
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{
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.name = "4Km",
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.CP0_PRid = 0x00018300,
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/* Config1 implemented, fixed mapping MMU,
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no virtual icache, uncached coherency. */
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.CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_FMT << CP0C0_MT),
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.CP0_Config1 = MIPS_CONFIG1 |
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(0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
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(0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
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(1 << CP0C1_CA),
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.CP0_Config2 = MIPS_CONFIG2,
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.CP0_Config3 = MIPS_CONFIG3,
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.CP0_LLAddr_rw_bitmask = 0,
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.CP0_LLAddr_shift = 4,
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.SYNCI_Step = 32,
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.CCRes = 2,
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.CP0_Status_rw_bitmask = 0x1258FF17,
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.SEGBITS = 32,
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.PABITS = 32,
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.insn_flags = CPU_MIPS32 | ASE_MIPS16,
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.mmu_type = MMU_TYPE_FMT,
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},
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{
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.name = "4KEcR1",
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.CP0_PRid = 0x00018400,
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.CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_R4000 << CP0C0_MT),
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.CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
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(0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
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(0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
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(0 << CP0C1_CA),
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.CP0_Config2 = MIPS_CONFIG2,
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.CP0_Config3 = MIPS_CONFIG3,
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.CP0_LLAddr_rw_bitmask = 0,
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.CP0_LLAddr_shift = 4,
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.SYNCI_Step = 32,
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.CCRes = 2,
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.CP0_Status_rw_bitmask = 0x1278FF17,
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.SEGBITS = 32,
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.PABITS = 32,
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.insn_flags = CPU_MIPS32,
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.mmu_type = MMU_TYPE_R4000,
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},
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{
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.name = "4KEmR1",
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.CP0_PRid = 0x00018500,
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.CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_FMT << CP0C0_MT),
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.CP0_Config1 = MIPS_CONFIG1 |
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(0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
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(0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
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(1 << CP0C1_CA),
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.CP0_Config2 = MIPS_CONFIG2,
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.CP0_Config3 = MIPS_CONFIG3,
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.CP0_LLAddr_rw_bitmask = 0,
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.CP0_LLAddr_shift = 4,
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.SYNCI_Step = 32,
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.CCRes = 2,
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.CP0_Status_rw_bitmask = 0x1258FF17,
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.SEGBITS = 32,
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.PABITS = 32,
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.insn_flags = CPU_MIPS32 | ASE_MIPS16,
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.mmu_type = MMU_TYPE_FMT,
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},
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{
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.name = "4KEc",
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.CP0_PRid = 0x00019000,
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.CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
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(MMU_TYPE_R4000 << CP0C0_MT),
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.CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
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(0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
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(0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
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(0 << CP0C1_CA),
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.CP0_Config2 = MIPS_CONFIG2,
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.CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
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.CP0_LLAddr_rw_bitmask = 0,
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.CP0_LLAddr_shift = 4,
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.SYNCI_Step = 32,
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.CCRes = 2,
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.CP0_Status_rw_bitmask = 0x1278FF17,
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.SEGBITS = 32,
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.PABITS = 32,
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.insn_flags = CPU_MIPS32R2,
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.mmu_type = MMU_TYPE_R4000,
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},
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{
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.name = "4KEm",
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.CP0_PRid = 0x00019100,
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.CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
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(MMU_TYPE_FMT << CP0C0_MT),
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.CP0_Config1 = MIPS_CONFIG1 |
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(0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
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(0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
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(1 << CP0C1_CA),
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.CP0_Config2 = MIPS_CONFIG2,
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.CP0_Config3 = MIPS_CONFIG3,
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.CP0_LLAddr_rw_bitmask = 0,
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.CP0_LLAddr_shift = 4,
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.SYNCI_Step = 32,
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.CCRes = 2,
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.CP0_Status_rw_bitmask = 0x1258FF17,
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.SEGBITS = 32,
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.PABITS = 32,
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.insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
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.mmu_type = MMU_TYPE_FMT,
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},
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{
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.name = "24Kc",
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.CP0_PRid = 0x00019300,
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.CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
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(MMU_TYPE_R4000 << CP0C0_MT),
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.CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
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(0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
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(0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
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(1 << CP0C1_CA),
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.CP0_Config2 = MIPS_CONFIG2,
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.CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
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.CP0_LLAddr_rw_bitmask = 0,
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.CP0_LLAddr_shift = 4,
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.SYNCI_Step = 32,
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.CCRes = 2,
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/* No DSP implemented. */
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.CP0_Status_rw_bitmask = 0x1278FF1F,
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.SEGBITS = 32,
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.PABITS = 32,
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.insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
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.mmu_type = MMU_TYPE_R4000,
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},
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{
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.name = "24Kf",
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.CP0_PRid = 0x00019300,
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.CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
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(MMU_TYPE_R4000 << CP0C0_MT),
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.CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
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(0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
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(0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
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(1 << CP0C1_CA),
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.CP0_Config2 = MIPS_CONFIG2,
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.CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
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.CP0_LLAddr_rw_bitmask = 0,
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.CP0_LLAddr_shift = 4,
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.SYNCI_Step = 32,
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.CCRes = 2,
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/* No DSP implemented. */
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.CP0_Status_rw_bitmask = 0x3678FF1F,
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.CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
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(1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
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.SEGBITS = 32,
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.PABITS = 32,
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.insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
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.mmu_type = MMU_TYPE_R4000,
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},
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{
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.name = "34Kf",
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.CP0_PRid = 0x00019500,
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.CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
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(MMU_TYPE_R4000 << CP0C0_MT),
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.CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
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(0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
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(0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
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(1 << CP0C1_CA),
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.CP0_Config2 = MIPS_CONFIG2,
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.CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_VInt) | (1 << CP0C3_MT) |
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(1 << CP0C3_DSPP),
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.CP0_LLAddr_rw_bitmask = 0,
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.CP0_LLAddr_shift = 0,
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.SYNCI_Step = 32,
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.CCRes = 2,
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.CP0_Status_rw_bitmask = 0x3778FF1F,
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.CP0_TCStatus_rw_bitmask = (0 << CP0TCSt_TCU3) | (0 << CP0TCSt_TCU2) |
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(1 << CP0TCSt_TCU1) | (1 << CP0TCSt_TCU0) |
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(0 << CP0TCSt_TMX) | (1 << CP0TCSt_DT) |
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(1 << CP0TCSt_DA) | (1 << CP0TCSt_A) |
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(0x3 << CP0TCSt_TKSU) | (1 << CP0TCSt_IXMT) |
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(0xff << CP0TCSt_TASID),
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.CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
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(1 << FCR0_D) | (1 << FCR0_S) | (0x95 << FCR0_PRID),
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.CP0_SRSCtl = (0xf << CP0SRSCtl_HSS),
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.CP0_SRSConf0_rw_bitmask = 0x3fffffff,
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.CP0_SRSConf0 = (1U << CP0SRSC0_M) | (0x3fe << CP0SRSC0_SRS3) |
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(0x3fe << CP0SRSC0_SRS2) | (0x3fe << CP0SRSC0_SRS1),
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.CP0_SRSConf1_rw_bitmask = 0x3fffffff,
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.CP0_SRSConf1 = (1U << CP0SRSC1_M) | (0x3fe << CP0SRSC1_SRS6) |
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(0x3fe << CP0SRSC1_SRS5) | (0x3fe << CP0SRSC1_SRS4),
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.CP0_SRSConf2_rw_bitmask = 0x3fffffff,
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.CP0_SRSConf2 = (1U << CP0SRSC2_M) | (0x3fe << CP0SRSC2_SRS9) |
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(0x3fe << CP0SRSC2_SRS8) | (0x3fe << CP0SRSC2_SRS7),
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.CP0_SRSConf3_rw_bitmask = 0x3fffffff,
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.CP0_SRSConf3 = (1U << CP0SRSC3_M) | (0x3fe << CP0SRSC3_SRS12) |
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(0x3fe << CP0SRSC3_SRS11) | (0x3fe << CP0SRSC3_SRS10),
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.CP0_SRSConf4_rw_bitmask = 0x3fffffff,
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.CP0_SRSConf4 = (0x3fe << CP0SRSC4_SRS15) |
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(0x3fe << CP0SRSC4_SRS14) | (0x3fe << CP0SRSC4_SRS13),
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.SEGBITS = 32,
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.PABITS = 32,
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.insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_MT,
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.mmu_type = MMU_TYPE_R4000,
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},
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{
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.name = "74Kf",
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.CP0_PRid = 0x00019700,
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.CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
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(MMU_TYPE_R4000 << CP0C0_MT),
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.CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
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(0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
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(0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
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(1 << CP0C1_CA),
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.CP0_Config2 = MIPS_CONFIG2,
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.CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_DSP2P) | (1 << CP0C3_DSPP) |
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(1 << CP0C3_VInt),
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.CP0_LLAddr_rw_bitmask = 0,
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.CP0_LLAddr_shift = 4,
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.SYNCI_Step = 32,
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.CCRes = 2,
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.CP0_Status_rw_bitmask = 0x3778FF1F,
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.CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
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(1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
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.SEGBITS = 32,
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.PABITS = 32,
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.insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_DSPR2,
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.mmu_type = MMU_TYPE_R4000,
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},
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{
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.name = "M14K",
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.CP0_PRid = 0x00019b00,
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/* Config1 implemented, fixed mapping MMU,
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no virtual icache, uncached coherency. */
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.CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_KU) | (0x2 << CP0C0_K23) |
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(0x1 << CP0C0_AR) | (MMU_TYPE_FMT << CP0C0_MT),
|
|
.CP0_Config1 = MIPS_CONFIG1,
|
|
.CP0_Config2 = MIPS_CONFIG2,
|
|
.CP0_Config3 = MIPS_CONFIG3 | (0x2 << CP0C3_ISA) | (1 << CP0C3_VInt),
|
|
.CP0_LLAddr_rw_bitmask = 0,
|
|
.CP0_LLAddr_shift = 4,
|
|
.SYNCI_Step = 32,
|
|
.CCRes = 2,
|
|
.CP0_Status_rw_bitmask = 0x1258FF17,
|
|
.SEGBITS = 32,
|
|
.PABITS = 32,
|
|
.insn_flags = CPU_MIPS32R2 | ASE_MICROMIPS,
|
|
.mmu_type = MMU_TYPE_FMT,
|
|
},
|
|
{
|
|
.name = "M14Kc",
|
|
/* This is the TLB-based MMU core. */
|
|
.CP0_PRid = 0x00019c00,
|
|
.CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
|
|
(MMU_TYPE_R4000 << CP0C0_MT),
|
|
.CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
|
|
(0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
|
|
(0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),
|
|
.CP0_Config2 = MIPS_CONFIG2,
|
|
.CP0_Config3 = MIPS_CONFIG3 | (0x2 << CP0C3_ISA) | (0 << CP0C3_VInt),
|
|
.CP0_LLAddr_rw_bitmask = 0,
|
|
.CP0_LLAddr_shift = 4,
|
|
.SYNCI_Step = 32,
|
|
.CCRes = 2,
|
|
.CP0_Status_rw_bitmask = 0x1278FF17,
|
|
.SEGBITS = 32,
|
|
.PABITS = 32,
|
|
.insn_flags = CPU_MIPS32R2 | ASE_MICROMIPS,
|
|
.mmu_type = MMU_TYPE_R4000,
|
|
},
|
|
{
|
|
/* A generic CPU providing MIPS32 Release 5 features.
|
|
FIXME: Eventually this should be replaced by a real CPU model. */
|
|
.name = "mips32r5-generic",
|
|
.CP0_PRid = 0x00019700,
|
|
.CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
|
|
(MMU_TYPE_R4000 << CP0C0_MT),
|
|
.CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
|
|
(0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
|
|
(0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
|
|
(1 << CP0C1_CA),
|
|
.CP0_Config2 = MIPS_CONFIG2,
|
|
.CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_MSAP),
|
|
.CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M),
|
|
.CP0_Config4_rw_bitmask = 0,
|
|
.CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_UFR),
|
|
.CP0_Config5_rw_bitmask = (0 << CP0C5_M) | (1 << CP0C5_K) |
|
|
(1 << CP0C5_CV) | (0 << CP0C5_EVA) |
|
|
(1 << CP0C5_MSAEn) | (1 << CP0C5_UFR) |
|
|
(0 << CP0C5_NFExists),
|
|
.CP0_LLAddr_rw_bitmask = 0,
|
|
.CP0_LLAddr_shift = 4,
|
|
.SYNCI_Step = 32,
|
|
.CCRes = 2,
|
|
.CP0_Status_rw_bitmask = 0x3778FF1F,
|
|
.CP1_fcr0 = (1 << FCR0_UFRP) | (1 << FCR0_F64) | (1 << FCR0_L) |
|
|
(1 << FCR0_W) | (1 << FCR0_D) | (1 << FCR0_S) |
|
|
(0x93 << FCR0_PRID),
|
|
.SEGBITS = 32,
|
|
.PABITS = 32,
|
|
.insn_flags = CPU_MIPS32R5 | ASE_MIPS16 | ASE_MSA,
|
|
.mmu_type = MMU_TYPE_R4000,
|
|
},
|
|
#if defined(TARGET_MIPS64)
|
|
{
|
|
.name = "R4000",
|
|
.CP0_PRid = 0x00000400,
|
|
/* No L2 cache, icache size 8k, dcache size 8k, uncached coherency. */
|
|
.CP0_Config0 = (1 << 17) | (0x1 << 9) | (0x1 << 6) | (0x2 << CP0C0_K0),
|
|
/* Note: Config1 is only used internally, the R4000 has only Config0. */
|
|
.CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
|
|
.CP0_LLAddr_rw_bitmask = 0xFFFFFFFF,
|
|
.CP0_LLAddr_shift = 4,
|
|
.SYNCI_Step = 16,
|
|
.CCRes = 2,
|
|
.CP0_Status_rw_bitmask = 0x3678FFFF,
|
|
/* The R4000 has a full 64bit FPU but doesn't use the fcr0 bits. */
|
|
.CP1_fcr0 = (0x5 << FCR0_PRID) | (0x0 << FCR0_REV),
|
|
.SEGBITS = 40,
|
|
.PABITS = 36,
|
|
.insn_flags = CPU_MIPS3,
|
|
.mmu_type = MMU_TYPE_R4000,
|
|
},
|
|
{
|
|
.name = "VR5432",
|
|
.CP0_PRid = 0x00005400,
|
|
/* No L2 cache, icache size 8k, dcache size 8k, uncached coherency. */
|
|
.CP0_Config0 = (1 << 17) | (0x1 << 9) | (0x1 << 6) | (0x2 << CP0C0_K0),
|
|
.CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
|
|
.CP0_LLAddr_rw_bitmask = 0xFFFFFFFFL,
|
|
.CP0_LLAddr_shift = 4,
|
|
.SYNCI_Step = 16,
|
|
.CCRes = 2,
|
|
.CP0_Status_rw_bitmask = 0x3678FFFF,
|
|
/* The VR5432 has a full 64bit FPU but doesn't use the fcr0 bits. */
|
|
.CP1_fcr0 = (0x54 << FCR0_PRID) | (0x0 << FCR0_REV),
|
|
.SEGBITS = 40,
|
|
.PABITS = 32,
|
|
.insn_flags = CPU_VR54XX,
|
|
.mmu_type = MMU_TYPE_R4000,
|
|
},
|
|
{
|
|
.name = "5Kc",
|
|
.CP0_PRid = 0x00018100,
|
|
.CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) |
|
|
(MMU_TYPE_R4000 << CP0C0_MT),
|
|
.CP0_Config1 = MIPS_CONFIG1 | (31 << CP0C1_MMU) |
|
|
(1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
|
|
(1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
|
|
(1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
|
|
.CP0_Config2 = MIPS_CONFIG2,
|
|
.CP0_Config3 = MIPS_CONFIG3,
|
|
.CP0_LLAddr_rw_bitmask = 0,
|
|
.CP0_LLAddr_shift = 4,
|
|
.SYNCI_Step = 32,
|
|
.CCRes = 2,
|
|
.CP0_Status_rw_bitmask = 0x12F8FFFF,
|
|
.SEGBITS = 42,
|
|
.PABITS = 36,
|
|
.insn_flags = CPU_MIPS64,
|
|
.mmu_type = MMU_TYPE_R4000,
|
|
},
|
|
{
|
|
.name = "5Kf",
|
|
.CP0_PRid = 0x00018100,
|
|
.CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) |
|
|
(MMU_TYPE_R4000 << CP0C0_MT),
|
|
.CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (31 << CP0C1_MMU) |
|
|
(1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
|
|
(1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
|
|
(1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
|
|
.CP0_Config2 = MIPS_CONFIG2,
|
|
.CP0_Config3 = MIPS_CONFIG3,
|
|
.CP0_LLAddr_rw_bitmask = 0,
|
|
.CP0_LLAddr_shift = 4,
|
|
.SYNCI_Step = 32,
|
|
.CCRes = 2,
|
|
.CP0_Status_rw_bitmask = 0x36F8FFFF,
|
|
/* The 5Kf has F64 / L / W but doesn't use the fcr0 bits. */
|
|
.CP1_fcr0 = (1 << FCR0_D) | (1 << FCR0_S) |
|
|
(0x81 << FCR0_PRID) | (0x0 << FCR0_REV),
|
|
.SEGBITS = 42,
|
|
.PABITS = 36,
|
|
.insn_flags = CPU_MIPS64,
|
|
.mmu_type = MMU_TYPE_R4000,
|
|
},
|
|
{
|
|
.name = "20Kc",
|
|
/* We emulate a later version of the 20Kc, earlier ones had a broken
|
|
WAIT instruction. */
|
|
.CP0_PRid = 0x000182a0,
|
|
.CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) |
|
|
(MMU_TYPE_R4000 << CP0C0_MT) | (1 << CP0C0_VI),
|
|
.CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (47 << CP0C1_MMU) |
|
|
(2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
|
|
(2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
|
|
(1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
|
|
.CP0_Config2 = MIPS_CONFIG2,
|
|
.CP0_Config3 = MIPS_CONFIG3,
|
|
.CP0_LLAddr_rw_bitmask = 0,
|
|
.CP0_LLAddr_shift = 0,
|
|
.SYNCI_Step = 32,
|
|
.CCRes = 1,
|
|
.CP0_Status_rw_bitmask = 0x36FBFFFF,
|
|
/* The 20Kc has F64 / L / W but doesn't use the fcr0 bits. */
|
|
.CP1_fcr0 = (1 << FCR0_3D) | (1 << FCR0_PS) |
|
|
(1 << FCR0_D) | (1 << FCR0_S) |
|
|
(0x82 << FCR0_PRID) | (0x0 << FCR0_REV),
|
|
.SEGBITS = 40,
|
|
.PABITS = 36,
|
|
.insn_flags = CPU_MIPS64 | ASE_MIPS3D,
|
|
.mmu_type = MMU_TYPE_R4000,
|
|
},
|
|
{
|
|
/* A generic CPU providing MIPS64 Release 2 features.
|
|
FIXME: Eventually this should be replaced by a real CPU model. */
|
|
.name = "MIPS64R2-generic",
|
|
.CP0_PRid = 0x00010000,
|
|
.CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
|
|
(MMU_TYPE_R4000 << CP0C0_MT),
|
|
.CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) |
|
|
(2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
|
|
(2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
|
|
(1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
|
|
.CP0_Config2 = MIPS_CONFIG2,
|
|
.CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA),
|
|
.CP0_LLAddr_rw_bitmask = 0,
|
|
.CP0_LLAddr_shift = 0,
|
|
.SYNCI_Step = 32,
|
|
.CCRes = 2,
|
|
.CP0_Status_rw_bitmask = 0x36FBFFFF,
|
|
.CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_3D) | (1 << FCR0_PS) |
|
|
(1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
|
|
(1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
|
|
.SEGBITS = 42,
|
|
/* The architectural limit is 59, but we have hardcoded 36 bit
|
|
in some places...
|
|
.PABITS = 59, */ /* the architectural limit */
|
|
.PABITS = 36,
|
|
.insn_flags = CPU_MIPS64R2 | ASE_MIPS3D,
|
|
.mmu_type = MMU_TYPE_R4000,
|
|
},
|
|
{
|
|
.name = "5KEc",
|
|
.CP0_PRid = 0x00018900,
|
|
.CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
|
|
(MMU_TYPE_R4000 << CP0C0_MT),
|
|
.CP0_Config1 = MIPS_CONFIG1 | (31 << CP0C1_MMU) |
|
|
(1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
|
|
(1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
|
|
(1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
|
|
.CP0_Config2 = MIPS_CONFIG2,
|
|
.CP0_Config3 = MIPS_CONFIG3,
|
|
.CP0_LLAddr_rw_bitmask = 0,
|
|
.CP0_LLAddr_shift = 4,
|
|
.SYNCI_Step = 32,
|
|
.CCRes = 2,
|
|
.CP0_Status_rw_bitmask = 0x12F8FFFF,
|
|
.SEGBITS = 42,
|
|
.PABITS = 36,
|
|
.insn_flags = CPU_MIPS64R2,
|
|
.mmu_type = MMU_TYPE_R4000,
|
|
},
|
|
{
|
|
.name = "5KEf",
|
|
.CP0_PRid = 0x00018900,
|
|
.CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
|
|
(MMU_TYPE_R4000 << CP0C0_MT),
|
|
.CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (31 << CP0C1_MMU) |
|
|
(1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
|
|
(1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
|
|
(1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
|
|
.CP0_Config2 = MIPS_CONFIG2,
|
|
.CP0_Config3 = MIPS_CONFIG3,
|
|
.CP0_LLAddr_rw_bitmask = 0,
|
|
.CP0_LLAddr_shift = 4,
|
|
.SYNCI_Step = 32,
|
|
.CCRes = 2,
|
|
.CP0_Status_rw_bitmask = 0x36F8FFFF,
|
|
.CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
|
|
(1 << FCR0_D) | (1 << FCR0_S) |
|
|
(0x89 << FCR0_PRID) | (0x0 << FCR0_REV),
|
|
.SEGBITS = 42,
|
|
.PABITS = 36,
|
|
.insn_flags = CPU_MIPS64R2,
|
|
.mmu_type = MMU_TYPE_R4000,
|
|
},
|
|
{
|
|
/* A generic CPU supporting MIPS64 Release 6 ISA.
|
|
FIXME: Support IEEE 754-2008 FP and misaligned memory accesses.
|
|
Eventually this should be replaced by a real CPU model. */
|
|
.name = "MIPS64R6-generic",
|
|
.CP0_PRid = 0x00010000,
|
|
.CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AR) | (0x2 << CP0C0_AT) |
|
|
(MMU_TYPE_R4000 << CP0C0_MT),
|
|
.CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) |
|
|
(2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
|
|
(2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
|
|
(0 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
|
|
.CP0_Config2 = MIPS_CONFIG2,
|
|
.CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_RXI) | (1 << CP0C3_BP) |
|
|
(1 << CP0C3_BI) | (1 << CP0C3_ULRI) | (1U << CP0C3_M),
|
|
.CP0_Config4 = MIPS_CONFIG4 | (0xfc << CP0C4_KScrExist) |
|
|
(3 << CP0C4_IE) | (1 << CP0C4_M),
|
|
.CP0_Config5_rw_bitmask = (1 << CP0C5_SBRI) | (1 << CP0C5_FRE) |
|
|
(1 << CP0C5_UFE),
|
|
.CP0_LLAddr_rw_bitmask = 0,
|
|
.CP0_LLAddr_shift = 0,
|
|
.SYNCI_Step = 32,
|
|
.CCRes = 2,
|
|
.CP0_Status_rw_bitmask = 0x30D8FFFF,
|
|
.CP0_PageGrain = (1 << CP0PG_IEC) | (1 << CP0PG_XIE) |
|
|
(1U << CP0PG_RIE),
|
|
.CP0_PageGrain_rw_bitmask = 0,
|
|
.CP1_fcr0 = (1 << FCR0_FREP) | (1 << FCR0_F64) | (1 << FCR0_L) |
|
|
(1 << FCR0_W) | (1 << FCR0_D) | (1 << FCR0_S) |
|
|
(0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
|
|
.SEGBITS = 42,
|
|
/* The architectural limit is 59, but we have hardcoded 36 bit
|
|
in some places...
|
|
.PABITS = 59, */ /* the architectural limit */
|
|
.PABITS = 36,
|
|
.insn_flags = CPU_MIPS64R6,
|
|
.mmu_type = MMU_TYPE_R4000,
|
|
},
|
|
{
|
|
.name = "Loongson-2E",
|
|
.CP0_PRid = 0x6302,
|
|
/* 64KB I-cache and d-cache. 4 way with 32 bit cache line size. */
|
|
.CP0_Config0 = (0x1<<17) | (0x1<<16) | (0x1<<11) | (0x1<<8) |
|
|
(0x1<<5) | (0x1<<4) | (0x1<<1),
|
|
/* Note: Config1 is only used internally,
|
|
Loongson-2E has only Config0. */
|
|
.CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
|
|
.SYNCI_Step = 16,
|
|
.CCRes = 2,
|
|
.CP0_Status_rw_bitmask = 0x35D0FFFF,
|
|
.CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV),
|
|
.SEGBITS = 40,
|
|
.PABITS = 40,
|
|
.insn_flags = CPU_LOONGSON2E,
|
|
.mmu_type = MMU_TYPE_R4000,
|
|
},
|
|
{
|
|
.name = "Loongson-2F",
|
|
.CP0_PRid = 0x6303,
|
|
/* 64KB I-cache and d-cache. 4 way with 32 bit cache line size. */
|
|
.CP0_Config0 = (0x1<<17) | (0x1<<16) | (0x1<<11) | (0x1<<8) |
|
|
(0x1<<5) | (0x1<<4) | (0x1<<1),
|
|
/* Note: Config1 is only used internally,
|
|
Loongson-2F has only Config0. */
|
|
.CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
|
|
.SYNCI_Step = 16,
|
|
.CCRes = 2,
|
|
.CP0_Status_rw_bitmask = 0xF5D0FF1F, /* Bits 7:5 not writable. */
|
|
.CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV),
|
|
.SEGBITS = 40,
|
|
.PABITS = 40,
|
|
.insn_flags = CPU_LOONGSON2F,
|
|
.mmu_type = MMU_TYPE_R4000,
|
|
},
|
|
{
|
|
/* A generic CPU providing MIPS64 ASE DSP 2 features.
|
|
FIXME: Eventually this should be replaced by a real CPU model. */
|
|
.name = "mips64dspr2",
|
|
.CP0_PRid = 0x00010000,
|
|
.CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
|
|
(MMU_TYPE_R4000 << CP0C0_MT),
|
|
.CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) |
|
|
(2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
|
|
(2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
|
|
(1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
|
|
.CP0_Config2 = MIPS_CONFIG2,
|
|
.CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_DSP2P) |
|
|
(1 << CP0C3_DSPP) | (1 << CP0C3_LPA),
|
|
.CP0_LLAddr_rw_bitmask = 0,
|
|
.CP0_LLAddr_shift = 0,
|
|
.SYNCI_Step = 32,
|
|
.CCRes = 2,
|
|
.CP0_Status_rw_bitmask = 0x37FBFFFF,
|
|
.CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_3D) | (1 << FCR0_PS) |
|
|
(1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
|
|
(1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
|
|
.SEGBITS = 42,
|
|
/* The architectural limit is 59, but we have hardcoded 36 bit
|
|
in some places...
|
|
.PABITS = 59, */ /* the architectural limit */
|
|
.PABITS = 36,
|
|
.insn_flags = CPU_MIPS64R2 | ASE_DSP | ASE_DSPR2,
|
|
.mmu_type = MMU_TYPE_R4000,
|
|
},
|
|
|
|
#endif
|
|
};
|
|
|
|
static const mips_def_t *cpu_mips_find_by_name (const char *name)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < ARRAY_SIZE(mips_defs); i++) {
|
|
if (strcasecmp(name, mips_defs[i].name) == 0) {
|
|
return &mips_defs[i];
|
|
}
|
|
}
|
|
return NULL;
|
|
}
|
|
|
|
void mips_cpu_list (FILE *f, fprintf_function cpu_fprintf)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < ARRAY_SIZE(mips_defs); i++) {
|
|
(*cpu_fprintf)(f, "MIPS '%s'\n",
|
|
mips_defs[i].name);
|
|
}
|
|
}
|
|
|
|
#ifndef CONFIG_USER_ONLY
|
|
static void no_mmu_init (CPUMIPSState *env, const mips_def_t *def)
|
|
{
|
|
env->tlb->nb_tlb = 1;
|
|
env->tlb->map_address = &no_mmu_map_address;
|
|
}
|
|
|
|
static void fixed_mmu_init (CPUMIPSState *env, const mips_def_t *def)
|
|
{
|
|
env->tlb->nb_tlb = 1;
|
|
env->tlb->map_address = &fixed_mmu_map_address;
|
|
}
|
|
|
|
static void r4k_mmu_init (CPUMIPSState *env, const mips_def_t *def)
|
|
{
|
|
env->tlb->nb_tlb = 1 + ((def->CP0_Config1 >> CP0C1_MMU) & 63);
|
|
env->tlb->map_address = &r4k_map_address;
|
|
env->tlb->helper_tlbwi = r4k_helper_tlbwi;
|
|
env->tlb->helper_tlbwr = r4k_helper_tlbwr;
|
|
env->tlb->helper_tlbp = r4k_helper_tlbp;
|
|
env->tlb->helper_tlbr = r4k_helper_tlbr;
|
|
env->tlb->helper_tlbinv = r4k_helper_tlbinv;
|
|
env->tlb->helper_tlbinvf = r4k_helper_tlbinvf;
|
|
}
|
|
|
|
static void mmu_init (CPUMIPSState *env, const mips_def_t *def)
|
|
{
|
|
MIPSCPU *cpu = mips_env_get_cpu(env);
|
|
|
|
env->tlb = g_malloc0(sizeof(CPUMIPSTLBContext));
|
|
|
|
switch (def->mmu_type) {
|
|
case MMU_TYPE_NONE:
|
|
no_mmu_init(env, def);
|
|
break;
|
|
case MMU_TYPE_R4000:
|
|
r4k_mmu_init(env, def);
|
|
break;
|
|
case MMU_TYPE_FMT:
|
|
fixed_mmu_init(env, def);
|
|
break;
|
|
case MMU_TYPE_R3000:
|
|
case MMU_TYPE_R6000:
|
|
case MMU_TYPE_R8000:
|
|
default:
|
|
cpu_abort(CPU(cpu), "MMU type not supported\n");
|
|
}
|
|
}
|
|
#endif /* CONFIG_USER_ONLY */
|
|
|
|
static void fpu_init (CPUMIPSState *env, const mips_def_t *def)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < MIPS_FPU_MAX; i++)
|
|
env->fpus[i].fcr0 = def->CP1_fcr0;
|
|
|
|
memcpy(&env->active_fpu, &env->fpus[0], sizeof(env->active_fpu));
|
|
}
|
|
|
|
static void mvp_init (CPUMIPSState *env, const mips_def_t *def)
|
|
{
|
|
env->mvp = g_malloc0(sizeof(CPUMIPSMVPContext));
|
|
|
|
/* MVPConf1 implemented, TLB sharable, no gating storage support,
|
|
programmable cache partitioning implemented, number of allocatable
|
|
and sharable TLB entries, MVP has allocatable TCs, 2 VPEs
|
|
implemented, 5 TCs implemented. */
|
|
env->mvp->CP0_MVPConf0 = (1U << CP0MVPC0_M) | (1 << CP0MVPC0_TLBS) |
|
|
(0 << CP0MVPC0_GS) | (1 << CP0MVPC0_PCP) |
|
|
// TODO: actually do 2 VPEs.
|
|
// (1 << CP0MVPC0_TCA) | (0x1 << CP0MVPC0_PVPE) |
|
|
// (0x04 << CP0MVPC0_PTC);
|
|
(1 << CP0MVPC0_TCA) | (0x0 << CP0MVPC0_PVPE) |
|
|
(0x00 << CP0MVPC0_PTC);
|
|
#if !defined(CONFIG_USER_ONLY)
|
|
/* Usermode has no TLB support */
|
|
env->mvp->CP0_MVPConf0 |= (env->tlb->nb_tlb << CP0MVPC0_PTLBE);
|
|
#endif
|
|
|
|
/* Allocatable CP1 have media extensions, allocatable CP1 have FP support,
|
|
no UDI implemented, no CP2 implemented, 1 CP1 implemented. */
|
|
env->mvp->CP0_MVPConf1 = (1U << CP0MVPC1_CIM) | (1 << CP0MVPC1_CIF) |
|
|
(0x0 << CP0MVPC1_PCX) | (0x0 << CP0MVPC1_PCP2) |
|
|
(0x1 << CP0MVPC1_PCP1);
|
|
}
|
|
|
|
static void msa_reset(CPUMIPSState *env)
|
|
{
|
|
#ifdef CONFIG_USER_ONLY
|
|
/* MSA access enabled */
|
|
env->CP0_Config5 |= 1 << CP0C5_MSAEn;
|
|
env->CP0_Status |= (1 << CP0St_CU1) | (1 << CP0St_FR);
|
|
#endif
|
|
|
|
/* MSA CSR:
|
|
- non-signaling floating point exception mode off (NX bit is 0)
|
|
- Cause, Enables, and Flags are all 0
|
|
- round to nearest / ties to even (RM bits are 0) */
|
|
env->active_tc.msacsr = 0;
|
|
|
|
restore_msa_fp_status(env);
|
|
|
|
/* tininess detected after rounding.*/
|
|
set_float_detect_tininess(float_tininess_after_rounding,
|
|
&env->active_tc.msa_fp_status);
|
|
|
|
/* clear float_status exception flags */
|
|
set_float_exception_flags(0, &env->active_tc.msa_fp_status);
|
|
|
|
/* clear float_status nan mode */
|
|
set_default_nan_mode(0, &env->active_tc.msa_fp_status);
|
|
}
|