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qemu-e2k/target/riscv/insn_trans
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Frank Chang cc13aa3614 target/riscv: rvv-1.0: Add ELEN checks for widening and narrowing instructions 
SEW has the limitation which cannot exceed ELEN.

Widening instructions have a destination group with EEW = 2*SEW
and narrowing instructions have a source operand with EEW = 2*SEW.
Both of the instructions have the limitation of: 2*SEW <= ELEN.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-78-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 		2021-12-20 14:53:31 +10:00
..
trans_privileged.c.inc target/riscv: Remove exit_tb and lookup_and_goto_ptr 2021-10-15 16:39:14 -07:00
trans_rva.c.inc target/riscv: Support pointer masking for RISC-V for i/c/f/d/a types of instructions 2021-10-28 14:39:23 +10:00
trans_rvb.c.inc target/riscv: Use gen_shift*_per_ol for RVB, RVI 2021-10-22 23:35:47 +10:00
trans_rvd.c.inc target/riscv: Support pointer masking for RISC-V for i/c/f/d/a types of instructions 2021-10-28 14:39:23 +10:00
trans_rvf.c.inc target/riscv: Support pointer masking for RISC-V for i/c/f/d/a types of instructions 2021-10-28 14:39:23 +10:00
trans_rvh.c.inc target/riscv: Tidy trans_rvh.c.inc 2021-09-01 11:59:12 +10:00
trans_rvi.c.inc target/riscv: Support pointer masking for RISC-V for i/c/f/d/a types of instructions 2021-10-28 14:39:23 +10:00
trans_rvm.c.inc target/riscv: Use gen_arith_per_ol for RVM 2021-10-22 23:35:43 +10:00
trans_rvv.c.inc target/riscv: rvv-1.0: Add ELEN checks for widening and narrowing instructions 2021-12-20 14:53:31 +10:00
trans_rvzfh.c.inc target/riscv: zfh: implement zfhmin extension 2021-12-20 14:51:36 +10:00